scispace - formally typeset
Search or ask a question

Showing papers by "Christian Szegedy published in 2007"


Proceedings ArticleDOI
05 Nov 2007
TL;DR: An implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times is presented and how to adapt this algorithm to logic optimization for timing correction at late stages of VLSI physical design is shown.
Abstract: We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We show how to adapt this algorithm to logic optimization for timing correction at late stages of VLSI physical design and report experimental results on recent industrial chips. By restructuring long critical paths, our code achieves worst-slack improvements of up to several hundred picoseconds on top of traditional timing optimization techniques.

24 citations


Patent
13 Aug 2007
TL;DR: In this article, the authors present methods, systems, and computer program products for performing grid morphing technique for computing a spreading of objects over an area such that the final locations of the objects are distributed over the area and such that their final locations are minimally perturbed from their initial starting locations and the density of objects meets certain constraints.
Abstract: Disclosed are methods, systems, and computer program products for performing grid morphing technique for computing a spreading of objects over an area such that the final locations of the objects are distributed over the area and such that the final locations of the objects are minimally perturbed from their initial starting locations and the density of objects meets certain constraints. The minimization of perturbation, or stability, of the approaches disclosed, is the key feature which is the principal benefit of the techniques disclosed. The methods described herein may be used as part of a tool for placement or floorplanning of logic gates or larger macroblocks for the design of an integrated circuit.

8 citations


Proceedings ArticleDOI
18 Mar 2007
TL;DR: This work proposes a novel placement approach called grid morphing, which is specifically tailored for an incremental approach to placement, and focuses on the stability of the placement,Which is critical for minimization of perturbation of the final placement under changes applied to the input netlist.
Abstract: Traditionally, research in global placement has focused on relatively few simple metrics, such as pure wirelength or routability estimates. However, in the real world today, designs are driven by not-so-simple issues such as timing and crosstalk. The future holds even more difficulties as physical models for devices and interconnects become increasingly complex and unpredictable. Adoption of an iterative methodology, where one incrementally fixes design errors, is a basic approach to tackling these problems. However, developers of placement algorithms have long neglected the need for an tool which can be easily adopted into an incremental design flow.We propose a novel placement approach called grid morphing, which is specifically tailored for an incremental approach to placement. In particular, our technique focuses on the stability of the placement, which is critical for minimization of perturbation of the final placement under changes applied to the input netlist. We comparethe stability of our approach to existing placement tools, and show through experiments that our approach still delivers good results under traditional placement metrics.

6 citations


Journal ArticleDOI
TL;DR: Let C be a circuit representing a straight-line program on n inputs x"1, x"2,...,x"n, where x"n" is the number of inputs and 1 is the power of the program.

6 citations