C
Christopher D. Thomas
Researcher at Intel
Publications - 16
Citations - 1571
Christopher D. Thomas is an academic researcher from Intel. The author has contributed to research in topics: Layer (electronics) & Gate oxide. The author has an hindex of 10, co-authored 16 publications receiving 1503 citations.
Papers
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Proceedings ArticleDOI
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
C. Auth,C. Allen,A. Blattner,Daniel B. Bergstrom,Mark R. Brazier,M. Bost,M. Buehler,V. Chikarmane,Tahir Ghani,Timothy E. Glassman,R. Grover,W. Han,D. Hanken,Michael L. Hattendorf,P. Hentges,R. Heussner,J. Hicks,D. Ingerly,Pulkit Jain,S. Jaloviar,Robert James,David Jones,J. Jopling,Subhash M. Joshi,C. Kenyon,Huichu Liu,R. McFadden,B. McIntyre,J. Neirynck,C. Parker,L. Pipes,Ian R. Post,S. Pradhan,M. Prince,S. Ramey,T. Reynolds,J. Roesler,J. Sandford,J. Seiple,Pete Smith,Christopher D. Thomas,D. Towner,T. Troeger,Cory E. Weber,P. Yashar,K. Zawadzki,Kaizad Mistry +46 more
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Patent
Semiconductor device using an interconnect
TL;DR: In this article, the effect of reducing electromigration in a metallization process is discussed, which includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first intermediateconnect; an upper interconnect that is either landed or unlanded and that is disposed above the first Interconnect; and an upper conductive diffuser layer disposed on the upper interconnection.
Patent
ELECTROLESS METHOD OF SEED LAYER DEPOSITION, REPAIR, AND FABRICATION OF Cu INTERCONNECTS
TL;DR: In this paper, a copper source, an environmentally friendly reducing agent, a pH buffer, a complexing agent, and a surfactant are formulated for both room temperature and elevated temperature operation.
Patent
Interconnect structures and a method of electroless introduction of interconnect structures
TL;DR: In this paper, an apparatus including a substrate comprising a device having contact point, a dielectric layer overlying the device with an opening to the contact point; and an interconnect structure disposed in the opening including an inter-connect material and a different conductive shunt material.
Patent
Method of making semiconductor device using an interconnect
TL;DR: In this article, the effect of reducing electromigration in a metallization process is discussed, which includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first intermediateconnect; an upper interconnect that is either landed or unlanded and that is disposed above the first Interconnect; and an upper conductive diffuser layer disposed on the upper interconnection.