Christopher F. Bull

Bio: Christopher F. Bull is an academic researcher from Texas Instruments. The author has contributed to research in topics: Power semiconductor device & Thermal resistance. The author has an hindex of 2, co-authored 2 publications receiving 46 citations.

Packaged power switching device

Abstract: A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof.

Novel thermally enhanced power package

Abstract: Heat generated in microelectronic devices as a result of dissipated power is a major issue in power electronics applications resulting in elevated application PC board temperatures. In order to minimize the down ward heat transfer to the application board an efficient method enabling the upward flow of heat from the silicon die to the top of the microelectronic package and subsequently transferred to the environment via forced convection needs to be employed [1]. The problem is that most of the current packaging technologies have a very poor junction-to-top thermal resistance so it is very difficult to have a substantial portion of the heat flowing to the top of the device [2]. In this paper we present a novel power package design that enables heat conduction to the top surface of the microelectronic package through the use of a high thermal conductivity path which reduces by more than a factor of ten the junction-to-top thermal resistance compared to standard solutions. The thermal resistance junction-to-top is found to be as low as 1 C/W, which is comparable with thermal resistance junction to board. This allows for a significant portion of the dissipated energy in the die to be conducted to the topside of the package where natural or forced convection can transfer the heat to the air. We discuss the design, manufacturability, performance and reliability of the package as well as thermal measurements which demonstrates the ability of the package to dissipate the heat. We also compare this solution with existing solution sin the marketplace.

Power device integration on a common substrate

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Integrating multi-output power converters having vertically stacked semiconductor chips

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance

Abstract: A power FET (100) comprising a leadframe including a pad (110), a first lead (111), and a second lead (112); a first metal clip (150) including a plate (150a), an extension (150b) and a ridge (150c), the plate and extension spaced from the leadframe pad and the ridge connected to the pad; a vertically assembled stack of FET chips in the space between the plate and the pad, the stack including a first n-channel FET chip (120) having the drain terminal on one surface and the source and gate terminals on the opposite surface, the drain terminal attached to the pad, the source terminal attached to a second clip (140) tied to the first lead; and a second n-channel FET chip (130) having the source terminal on one surface and the drain and gate terminals on the opposite surface, the source terminal attached to the second clip, its drain terminal attached to the first clip; wherein the drain-source on-resistance of the FET stack is smaller than the on-resistance of the first FET chip and of the second FET chip.

Three-Dimensional Power Supply Module Having Reduced Switch Node Ringing

Abstract: A high frequency power supply module ( 800 ) of a synchronous Buck converter having the control die ( 810 ) directly soldered drain-down to the pad ( 801 ) of a leadframe; pad ( 801 ) is connected to V IN and the V IN connection to control die ( 810 ) exhibits vanishing impedance and inductance, thus reducing the amplitude and duration of switch node voltage ringing by more than 90%. Consequently, the input current enters the control die terminal vertically from the pad. The switch node clip ( 840 ), topping the control die ( 810 ), is designed with an area large enough to place the sync die ( 820 ) drain-down on top of the control die; the current continues to flow vertically through the converter stack. The active area of the sync die is equal to or greater than the active area of the control die; the physical area of the sync die is equal to or greater than the physical area of the control die. The source terminal of sync die ( 820 ) is connected to ground by clip ( 860 ) designed to act as a heat spreader.

Method for fabricating stack die package

Abstract: In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.