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Christopher L. Hamlin

Bio: Christopher L. Hamlin is an academic researcher from LSI Corporation. The author has contributed to research in topics: Integrated circuit & Integrated circuit design. The author has an hindex of 6, co-authored 17 publications receiving 275 citations.

Papers
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Proceedings ArticleDOI
02 Jun 2003
TL;DR: A next-generation fabric is needed that will once again provide designers with “fast, cheap, and under control” implementation and how deeply must the concept of regularity be engrained in the silicon implementation fabric to enable adequate yield and cost control in the face of CD variation and high mask NRE cost.
Abstract: Overview The semiconductor industry is caught on two horns of the economics dilemma: (1) the economics of technology deepsubwavelength lithography and equipment cost, reticle enhancement technology and mask cost, and manufacturing variability and yield; and (2) the economics of design productivity design turnaround time, availability of design skills, and portability of design effort. Standard-cells and the RTL methodology have taken us into the 90nm generation, but design is slow, expensive, and out of control. What we need is a next-generation fabric that will once again provide designers with “fast, cheap, and under control” implementation. The question: which fabric? How deeply must the concept of regularity be engrained in the silicon implementation fabric to enable adequate yield and cost control in the face of CD variation and high mask NRE cost? Via-programmable fabrics such as eASIC (VPGA) provide an intermediate design point in the cost-density-performance space, but is this offering sufficiently attractive (let alone defensible)? Or, will traditional FPGAs continue to take up more of the market, starting from their foothold in low-volume and/or reconfigurable applications? On the other hand, regularity and programmability incur cost and performance losses as they abandon the leading edge of the scaling curve. Are such losses growing, and will we therefore always see viable ASIC and COT businesses? Finally, what are the views and needs of the platform SOC and pure-play foundry constituencies?

155 citations

Patent
23 Jul 2003
TL;DR: In this paper, a system for providing distributed dynamic functionality in an electronic environment may include a plurality of platforms, suitable for providing a logic function, and include embedded programmable logic, memory and a reconfigurable core.
Abstract: The present invention is directed to platform architecture. A system for providing distributed dynamic functionality in an electronic environment may include a plurality of platforms. The platforms are suitable for providing a logic function, and include embedded programmable logic, memory and a reconfigurable core. The logic, memory and reconfigurable core are communicatively coupled via a fabric interconnect. A map is also included which expresses logic functions of the plurality of platforms.

31 citations

Patent
29 Jan 2004
TL;DR: In this article, a method for mapping platform-based design to multiple foundry processes may include the following steps: first, a virtual process is defined to include at least one fabrication process.
Abstract: The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a method for mapping platform-based design to multiple foundry processes may include the following steps. First, a virtual process is defined to include at least one fabrication process. A virtual process is a totality of variables associated with the population of candidate processes and any other process of interest, which might be purely hypothetical, that would be capable, in principle, of accommodating some or all slices. A virtual process may or may not be realized and is an abstract logical container for a population of processes. Then, the virtual process may be stored into a database. The virtual process may be in a representation including a list of attributes of entities making up the fabrication process. Next, optimization of the database may be performed using mathematical and statistical tools.

29 citations

Patent
01 Feb 2002
TL;DR: In this paper, a system for providing distributed functionality in an electronic environment includes a plurality of platforms suitable for providing a logic function, including embedded programmable logic, and MRAM memory, the logic and memory communicatively coupled via an interconnect.
Abstract: The present invention is directed to magnetoresistive memory and data storage devices. A system for providing distributed functionality in an electronic environment includes a plurality of platforms suitable for providing a logic function. The platforms include embedded programmable logic, and MRAM memory, the logic and MRAM memory communicatively coupled via an interconnect.

15 citations

Patent
30 Jan 2004
TL;DR: In this article, the authors present a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets.
Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

10 citations


Cited by
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Patent
08 Mar 2007
TL;DR: In this paper, a linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrodes segments within the linear-gated electrode track, while ensuring adequate electrical isolation between the adjacent linear gated electrode segments.
Abstract: A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

217 citations

Patent
01 Apr 2005
TL;DR: In this article, a Wafer Image Modeling and Prediction System (WIMAPS) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (RET) and printing processes in integrated circuit (IC) fabrication.
Abstract: A Wafer Image Modeling and Prediction System (“WIMAPS”) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in integrated circuit (“IC”) fabrication. The WIMAPS provides efficient processes for use by designers in predicting the RET and wafer printing process so as to allow designers to filter predict printed silicon contours prior to application of RET and printing processes to the circuit design.

196 citations

Patent
11 Jan 2008
TL;DR: In this paper, a method for defining a dynamic array section to be manufactured on a semiconductor chip is described, which includes defining a peripheral boundary of the dynamic array and a manufacturing assurance halo outside the boundary.
Abstract: A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo.

163 citations

Proceedings ArticleDOI
06 Mar 2006
TL;DR: This paper addresses the verification issue with a methodology and fabric to directly tie FPGA prototype and functional in-system verification with a clean migration path to structured ASIC.
Abstract: Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address the verification issue with a methodology and fabric to directly tie FPGA prototype and functional in-system verification with a clean migration path to structured ASIC. The most important aspects of this methodology are the use of physically identical blocks for difficult-to-verify PLLs, I/O and RAM and a structured re-synthesis of FPGA logic blocks to target cells that guarantees anchor points for easy formal verification.

161 citations

Patent
07 Mar 2009
TL;DR: In this article, the vertical connection structures are placed at a number of gridpoints within a vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels.
Abstract: First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size. The vertical connection structures may be contacts or vias.

152 citations