We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method, therefore, yields completely automated sizing of (globally) optimal CMOS amplifiers, directly from specifications. In this paper, we apply this method to a specific widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can he used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.

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Optimal design of a CMOS op-amp via geometric programming

This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease.

Transistor matching in analog CMOS applications

Traditionally, work on analog testing has focused on diagnosing faults in board designs. Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem. Analog blocks embedded in digital systems may not easily be separately testable. Consequently, many papers have been recently written proposing techniques to reduce the burden of testing analog and mined-signal circuits. This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.

A tutorial introduction to research on analog and mixed-signal circuit testing

A large-scale monolithic silicon nanophotonic phased array on a chip creates and dynamically steers a high-resolution optical beam in free space, enabling emerging applications in sensing, imaging, and communication. The scalable architecture leverages sub-array structure, mitigating the impact of process variation on the phased array performance. In addition, sharing control electronics among multiple optical modulators in the scalable architecture reduces the number of digital-to-analog converters (DACs) required for an $N^{2}$ array from $\mathcal {O}(N^{2})$ to $\mathcal {O}(N)$ , allowing a small silicon footprint. An optical phased array for 1550-nm wavelength with 1024 uniformly spaced optical grating antennas, 1192 optical variable phase shifters, and 168 optical variable attenuators is integrated into a 5.7 mm $\times$ 6.4 mm chip in a commercial 180-nm silicon-on-insulator RF CMOS technology. The control signals for the optical variable phase shifters and attenuators are provided by 136 DACs with 14-bit nonuniform resolution using 2.5-V input-output transistors. The implemented phased array can create 0.03° narrow optical beams that can be steered unambiguously within ±22.5°.

A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS

A unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented. The net input signals are currents instead of voltages, which avoids the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploiting current mirror properties for the efficient implementation of both linear and nonlinear analog operators. Basic design issues, the influence of nonidealities and advanced circuit design issues, and design for manufacturability considerations associated with statistical analysis are discussed. Experimental results are given for three prototypes designed for 1.6- mu m n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. >

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Current-mode techniques for the implementation of continuous- and discrete-time cellular neural networks

A generalized parameter-level statistical model, called statistical MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo approach to parameter sampling, circuit output means and standard deviations can be simulated. Incorporated in a CAD environment, these modeling algorithms will provide the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Test chips have been fabricated from two different fabrication processes to extract statistical information required by the model. Experimental and simulation results for two analog subcircuits are compared to verify the statistical modeling algorithms. >

Statistical modeling of device mismatch for analog MOS integrated circuits

The use of a four-parameter MOS model to characterize drain current mismatch is discussed. Guidelines for the accurate and repeatable measurement of transistor parameter mismatch are presented, along with two extraction methodologies based upon these guidelines. Parameter mismatch measurements made on 430 NMOS and 430 PMOS transistor pairs fabricated in a 0.8-/spl mu/m process are used to predict the drain current mismatch of the same population of transistors. Comparisons are made between the predicted and measured values. >

Characterization of transistor mismatch for statistical CAD of submicron CMOS analog circuits

A new statistical MOS model has been developed for computer-aided design of submicrometer analog integrated circuits. This model accounts for both parameter mismatch and inter-die parameter variations, both of which contribute to statistical variations in analog circuit performance. New characterization methods were developed to improve model fit to parameter standard deviations over a broad range of transistor biases. Implementation of this model in HSPICE is demonstrated, meaning that no exotic simulation tools are required to perform the statistical simulations. The model was tested on a 0.8 /spl mu/m CMOS process, with simulated and measured values of drain current variability showing excellent agreement.

A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits

In this paper, we present a statistical constrained CAD-compatible optimization algorithm for analog MOS integrated circuit design. The algorithm uses design of experiments (DOE), together with the response surface methodology (RSM), to determine simple empirical models relating circuit performances to device sizes. It then applies the Lagrange multiplier method to solve the resulting statistical constrained nonlinear optimization problem. The algorithm is guaranteed to converge to the global minimum. Using this new algorithm, we show that the transistors which cause variations in the performances of a two-stage op-amp can be identified and resized in an area-efficient manner to meet performance specifications. >

Statistical constrained optimization of analog MOS circuits using empirical performance models

A low cost method of producing proper source/drain junctions and transistor characteristics is disclosed. Through consolidation of masking steps, source/drain processing has a significantly lower cost with no performance loss. A blanket boron implant is employed as both a PLDD implant for the PMOS and a halo region implant for the NMOS. After formation of sidewall spacers on the gates, a masked arsenic and phosphorous implant is employed as a N+ implant. Because the phosphorous drives in faster than the arsenic, the desired N+/NLDD/halo architecture is generated. A masked boron implant is then employed as the P+ implant. Thus, the source/drain junctions are formed using only two masked implants. In an alternative embodiment, a third masked implant of phosphorous is used to form the NLDD junction prior to the sidewall spacer deposition instead of phosphorous being implanted with the arsenic.

Christopher Michael

Papers

Statistical modeling of device mismatch for analog MOS integrated circuits

Characterization of transistor mismatch for statistical CAD of submicron CMOS analog circuits

A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits

Statistical constrained optimization of analog MOS circuits using empirical performance models

Low cost deep sub-micron CMOS process