Chulsoo Park

Bio: Chulsoo Park is an academic researcher from Seoul National University. The author has contributed to research in topics: Design space exploration & Application domain. The author has an hindex of 4, co-authored 4 publications receiving 199 citations.

Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization

Abstract: Coarse-grained reconfigurable architectures aim to achieve both goals of high performance and flexibility. However, existing reconfigurable array architectures require many resources without considering the specific application domain. Functional resources that take long latency and/or large area can be pipelined and/or shared among the processing elements. Therefore the hardware cost and the delay can be effectively reduced without any performance degradation for some application domains. We suggest such reconfigurable array architecture template and design space exploration flow for domain-specific optimization. Experimental results show that our approach is much more efficient both in performance and area compared to existing reconfigurable architectures.

Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization

Abstract: Coarse-grained reconfigurable architectures aim to achieve goals of both high performance and flexibility. However, existing reconfigurable array architectures require many resources without considering the specific application domain. Functional resources that take long latency and/or large area can be pipelined and/or shared among the processing elements. Therefore, the hardware cost and the delay can be effectively reduced without any performance degradation for some application domains. We suggest such a reconfigurable array architecture template and a design space exploration flow for domain-specific optimization. Experimental results show that our approach is much more efficient, in both performance and area, compared to existing reconfigurable architectures.

Design and Evaluation of a Coarse-Grained Reconfigurable Architecture

Abstract: Coarse-grained reconfigurable architectures have become more attractive with the increasing requirement of more flexibility and higher performance in embedded systems design. In this paper, we suggest a design space exploration flow that enables effective optimization of reconfigurable architectures through SystemC Modeling. In the suggested flow, application-to-architecture mapping process tries loop pipelining technique to find a better performance. According to the result of design space exploration, we implement a coarse-grained reconfigurable architecture in RT level. For the evaluation, we take H.263 encoder as the application. Estimated results show significant improvement over previous approaches.

Chip Implementation of a Coarse-Grained Reconfigurable Architecture

Abstract: This paper presents coarse-grained reconfigurable architecture supporting floating-point operations, where each integer processing element is paired with its neighbor to perform floating point operations. One processing element in a pair is in charge of the mantissa part, and the other is in charge of the exponent part. With an 8 times 2 array of processing elements, 8 floating-point operations can be performed at the same time. The chip is fabricated in MagnaChip/Hynix 0.18 mum technology with the gate count of 363,013 and clock frequency of 116.8 MHz in the typical case.

Coarse grained reconfigurable architectures in the past 25 years: Overview and classification

Abstract: Reconfigurable architectures become more popular now general purpose compute performance does not increase as rapidly as before. Field programmable gate arrays are slowly moving into the direction of Coarse Grain Reconfigurable Architectures (CGRA) by adding DSP and other coarse grained IP blocks, general purpose processors become more heterogeneous and include sub-word parallelism and even some reconfigurable logic. In the past 25 years, several CGRAs have been published. In this paper an overview and classification of these architectures is presented. This work also provides a clear definition of CGRAs and identifies topics for future research which are key to unlock the full potential of CGRAs.

Coarse-Grained Reconfigurable Array Architectures

Abstract: Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture

Abstract: Coarse-grained reconfigurable architecture aims to achieve both performance and flexibility. However, power consumption is no less important for the reconfigurable architecture to be used as a competitive processing core in embedded systems. In this paper, we show how power is consumed in a typical coarse-grained reconfigurable architecture. Based on the power breakdown data, we suggest a power-conscious configuration cache structure and code mapping technique, which reduce power consumption without performance degradation. Experimental results show that the proposed approach saves much power even with reduced configuration cache size.

FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability

Abstract: This paper demonstrates a chip implementation of coarse-grained reconfigurable architecture named FloRA. Two-dimensional array of integer processing elements in the FloRA is configured in run-time to perform integer functions as well as floating-point functions. FloRA is implemented in Dongbu HiTek 130nm process and evaluate by running applications including physics engine and jpeg decoder.

A Hybrid Estimator for Active/Reactive Power Control of Single-Phase Distributed Generation Systems With Energy Storage

Abstract: This paper presents a new active/reactive power closed-loop control system for a hybrid renewable energy generation system used for single-phase residential/commercial applications. The proposed active/reactive control method includes a hybrid estimator, which is able to quickly and accurately estimate the active/reactive power values. The proposed control system enables the hybrid renewable energy generation system to be able to perform real-time grid interconnection services such as active voltage regulation, active power control, and fault ride-through. Simulation and experimental results demonstrate the superior performance of the proposed closed-loop control system.