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Chunlei Wu
Researcher at Peking University
Publications - 51
Citations - 573
Chunlei Wu is an academic researcher from Peking University. The author has contributed to research in topics: Field-effect transistor & CMOS. The author has an hindex of 11, co-authored 49 publications receiving 477 citations.
Papers
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Proceedings ArticleDOI
A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration
TL;DR: In this paper, a junction depleted-modulation design was proposed to achieve equivalently abrupt tunnel junction of Si tunnel FETs, which can reliably and effectively achieve much steeper switching behavior and higher ON current without area penalty and special fabrication compared with traditional TFET.
Journal ArticleDOI
An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs
TL;DR: In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified, and the transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively.
Journal ArticleDOI
A Novel Tunnel FET Design With Stacked Source Configuration for Average Subthreshold Swing Reduction
TL;DR: In this paper, a novel heterostacked tunnel FET (HS-TFET) is proposed for steeper average sub-threshold swing (SS), which owns a stacked source configuration consisting of an upper source layer with a relatively larger bandgap material and an underlying layer with smaller bandgap materials.
Proceedings ArticleDOI
Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective
Qianqian Huang,Ru Huang,Chunlei Wu,Zhu Hao,Cheng Chen,Jiaxin Wang,Lingyi Guo,Runsheng Wang,Le Ye,Yangyuan Wang +9 more
TL;DR: In this paper, a pocket-mSTFET (PMS-TFET) is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications.
Proceedings ArticleDOI
First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap
Qianqian Huang,Rundong Jia,Cheng Chen,Zhu Hao,Lingyi Guo,Junyao Wang,Jiaxin Wang,Chunlei Wu,Runsheng Wang,Weihai Bu,Jing Kang,Wenbo Wang,Hanming Wu,Shiuh-Wuu Lee,Yangyuan Wang,Ru Huang +15 more
TL;DR: In this paper, complementary tunnel-FETs (C-TFETs) are integrated with CMOS foundry for high volume production, demonstrating an intrinsic tradeoff between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs.