Chunyu Zhou

Bio: Chunyu Zhou is an academic researcher from Xidian University. The author has contributed to research in topics: BiCMOS & Heterojunction bipolar transistor. The author has an hindex of 4, co-authored 36 publications receiving 55 citations.

Double-gate tunnel field-effect transistor: Gate threshold voltage modeling and extraction

Abstract: The tunnel field-effect transistor (TFET) is a potential candidate for the post-CMOS era. As one of the most important electrical parameters of a device, double gate TFET (DG-TFET) gate threshold voltage was studied. First, a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported. Then, a simple analytical model for DG-TFET gate threshold voltage V TG was built by solving quasi-two-dimensional Poisson equation in Si film. The model as a function of the drain voltage, the Si layer thickness, the gate length and the gate dielectric was discussed. It is shown that the proposed model is consistent with the simulation results. This model should be useful for further investigation of performance of circuits containing TFETs.

Analytical model for quasi-static C–V characteristics of strained-Si/SiGe pMOS capacitor

Abstract: An analytical model for quasi-static C – V characteristics of strained-Si/SiGe pMOS capacitor is presented. By analyzing the model, the dependence of the C – V characteristics on the strained-Si layer thickness, doping concentration and Ge fraction is studied. Also, the reason of the shift of the plateau, observed in the gate C – V characteristics of the strained-Si pMOS capacitor, from the inversion region to the accumulation region as doping concentration increasing, has been explained. The results from the models show excellent agreement with the simulations and experimental data. The proposed models can be used to guide the design and has been implemented in the software for extracting the parameter of strained-Si MOSFET.

Longitudinal, transverse, density-of-states, and conductivity masses of electrons in (001), (101) and (111) biaxially-strained-Si and strained-Si 1− x Ge x

Abstract: In this study, the electron effective masses, including longitudinal, transverse, density-of-states and conductivity effective masses, have been systematically investigated in (001), (101) and (111) biaxially strained Si and Si1−xGex. It is found that the effect of strain on the longitudinal and transverse masses can be neglected, that the density-of-states masses in (001) and (110) biaxially strained Si and Si1−xGex materials decrease significantly with increasing Ge fraction (x), and that the conductivity masses along typical orientations in (001) and (110) strained Si and Si1−xGex.are obviously different from those in relaxed Si. The quantitative results obtained from this work may provide valuable theoretical references to understanding strained materials physics and studying conduction channel design related to stress and orientations in the strained devices.

Polycrystalline Si1-xGex/metal parallel covering double-gate strained SiGe-on-insulator (SSGOI) n metal oxide semiconductor field effect transistor (MOSFET) device structure

Abstract: The invention discloses a polycrystalline Si1-xGex/metal parallel covering double-gate stepped buried oxide strained SiGe-on-insulator (SSGOI) n metal oxide semiconductor field effect transistor (MOSFET) device structure. In the technical scheme, the device structure consists of a polycrystalline Si1-xGex/metal parallel covering double-gate structure, a gate insulating layer, an intrinsic or p-doped strain Si electronic quantum well layer, a p-doped relaxation Si1-yGey buffer layer, a stepped buried oxide layer and a p-doped substrate from top to bottom, wherein the p-doped monocrystalline Si(100) substrate consists of three parts, namely a p-relaxation Si1-yGey buffer layer, a p-relaxation SiGe gradient layer and monocrystalline Si. The device structure is simple and completely compatible with the conventional Si silicon-on-insulator (SOI) process, and integrates the advantages of grid engineering, strain engineering and substrate engineering.

Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

Abstract: A new analytical model for the gate threshold voltage ($$V_\mathrm{TG}$$VTG) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson's equation in the lightly doped Si film and employing the physical definition of $$V_\mathrm{TG}$$VTG. A numerical simulation study of the transfer characteristics and $$V_\mathrm{TG}$$VTG of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of $$V_\mathrm{TG}$$VTG is performed based on the transconductance change method as already used for conventional metal---oxide---semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on $$V_\mathrm{TG}$$VTG are reported. The dependence of $$V_\mathrm{TG}$$VTG on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.

Investigation of RF and linearity performance of electrode work-function engineered HDB vertical TFET

Abstract: This work realises a hetero-dielectric buried oxide vertical tunnel held effect transistor (HDB VTFET) and investigates its radio frequency (RF) and linearity characteristics. First time, the concept of hetero-dielectric buried oxide (BOX) in VTFET is used to obtain the superior improvement in terms of different RF and linearity hgure of merits such as C gs , C gd , C gg , f T , Gain Bandwidth Product (GBP), t, Transconductance Frequency Product (TFP), Transconductance Generation Factor (TGF), g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , IMD 3 and 1-dB compression point. Also, the influence of HfO2 BOX length scaling on these FOMs is analysed. The results reveal that the HDB VTFET can be a promising contender to replace bulk metal-oxide semiconductor held-effect transistors in analogue/mixed signal system-on-chip and high-frequency microwave applications and the accuracy of this device is validated by TCAD Sentaurus simulator.

Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

Abstract: A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gauss's law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.

MOS Devices with Non-Uniform P-type Impurity Profile

Abstract: An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.