Clement Pribat

Bio: Clement Pribat is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Thermal oxidation & Oxide. The author has an hindex of 4, co-authored 9 publications receiving 117 citations.

14nm FDSOI technology for high speed and energy efficient applications

Abstract: This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m 2 high-density bitcell and two 0.090°m 2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

Si and SiGe faceting during selective epitaxy

Abstract: Facet apparition during selective epitaxial growth of silicon and silicon–germanium alloys is reported in terms of morphology and kinetics. Epitaxial growth was performed on (0 0 1) Si wafers by chemical vapour deposition using the H2/HCl/SiH2Cl2 chemistry for silicon and GeH4 addition for silicon–germanium alloy. The (0 0 1) Si and SiGe growth rate was found to be limited by chlorine desorption at low temperature. The creation and development of (3 1 1) facets has been clearly explained by the epitaxial growth kinetics considerations. The impact of the deposition conditions, of the pattern structure and also of the dielectric nature on faceting are discussed here and analysed, thanks to cross section scanning electron microscopy (XSEM) and cross section transmission electron microscopy (XTEM) observations.

Oxidation kinetics of Si and SiGe by dry rapid thermal oxidation, in-situ steam generation oxidation and dry furnace oxidation

Abstract: The fabrication of ultrathin compressively strained SiGe-On-Insulator layers by the condensation technique is likely a key milestone towards low-power and high performances FD-SOI logic devices. However, the SiGe condensation technique still requires challenges to be solved for an optimized use in an industrial environment. SiGe oxidation kinetics, upon which the condensation technique is founded, has still not reached a consensus in spite of various studies which gave insights into the matter. This paper aims to bridge the gaps between these studies by covering various oxidation processes relevant to today's technological needs with a new and quantitative analysis methodology. We thus address oxidation kinetics of SiGe with three Ge concentrations (0%, 10%, and 30%) by means of dry rapid thermal oxidation, in-situ steam generation oxidation, and dry furnace oxidation. Oxide thicknesses in the 50 A to 150 A range grown with oxidation temperatures between 850 and 1100 °C were targeted. The present work shows first that for all investigated processes, oxidation follows a parabolic regime even for thin oxides, which indicates a diffusion-limited oxidation regime. We also observe that, for all investigated processes, the SiGe oxidation rate is systematically higher than that of Si. The amplitude of the variation of oxidation kinetics of SiGe with respect to Si is found to be strongly dependent on the process type. Second, a new quantitative analysis methodology of oxidation kinetics is introduced. This methodology allows us to highlight the dependence of oxidation kinetics on the Ge concentration at the oxidation interface, which is modulated by the pile-up mechanism. Our results show that the oxidation rate increases with the Ge concentration at the oxidation interface.

22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications

Abstract: 22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μΑ/μm (856μΑ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V V min for 8T logic libraries, as well as 0.62V and 0.52V V min for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm I off , and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high f T /f MAx of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high f MAx extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.

1.1 Silicon technologies and solutions for the data-driven world

Abstract: The remarkable evolution of human society over the centuries has been driven by information. As information became digitalized thanks to silicon technologies, creating, sharing, and searching of data have become much easier. Most recently, scaled silicon technology has been at the core of this information revolution, as it forms the basis on which digital devices, such as computers, smartphones, and tablets, are built. As the feature size of silicon technology approaches sub-10nm, there are concerns that it cannot satisfy the demand for high performance devices through scaling any longer. However, through innovations in materials, structures, and processes, it will continue to provide higher-performance components to electronics systems for the coming decades. With performance-enhancing technologies, such as 3D ICs and Through-Silicon Vias (TSVs), and systems technologies on servers, clients, and interconnections, the data-driven world will continue to expand in the future.

Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

Abstract: A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel lengths on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness.