Dynamic Partial Reconfiguration is an important feature of modern FPGAs as it allows for better exploitation of FPGA resources over time and space. The Internal Configuration Access Port (ICAP) enables DPR from within an FPGA chip, leading to the possibility of fully autonomous FPGA-based systems. This paper presents a novel high performance and fault-tolerant ICAP controller which can operate at a high speed and recover from emerging faults. Test results showed that our ICAP controller is 25 times faster than the Xilinx' XPS_HWICAP IP core. We demonstrate the use of Triple Modular Redundancy (TMR) in some of the ICAP controller components which have the ability to reconfigure the rest of the ICAP controller when faults are detected. This method is shown to have a 49% smaller area footprint compared to traditional full TMR.

A novel high-performance fault-tolerant ICAP controller

Processors are an essential component in most satellite payload electronics and handle a variety of functions including command handling and data processing. There is growing interest in implementing soft processors on commercial FPGAs within satellites. Commercial FPGAs offer reconfigurability, large logic density, and I/O bandwidth; however, they are sensitive to ionizing radiation and systems developed for space must implement single-event upset mitigation to operate reliably. This paper investigates the improvements in reliability of a LEON3 soft processor operating on a SRAM-based FPGA when using triple-modular redundancy and other processor-specific mitigation techniques. The improvements in reliability provided by these techniques are validated with both fault injection and heavy ion radiation tests. The fault injection experiments indicate an improvement of 51× and the radiation testing results demonstrate an average improvement of 10×. Orbit failure rate estimations were computed and suggest that the TMR LEON3 processor has a mean-time to failure of over 76 years in a geosynchronous orbit.

SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing

Cyber Physical Systems (CPSs), such as those found in modern vehicles, include a number of important time and safety-critical functions. Traditionally, applications are mapped to several dedicated electronic control units (ECUs), and hence, as new functions are added, compute weight and cost increase considerably.%ECU consolidation, where multiple functions are combined on fewer ECUs is an important area, but traditional software ECUs fail to offer the required performance, parallelism, and isolation to support this. With increasing computational and communication demands, traditional software ECUs fail to offer the required performance to provide determinism and predictability, while multi-core approaches fail to provide sufficient isolation between tasks. Hybrid FPGAs, combining a processor and reconfigurable fabric on a single die, allow for parallel hardware implementation of complex sensor processing tightly coupled with the flexibility of software on a processor. We demonstrate the advantages of such architectures in consolidating distributed processing with predictability, determinism and isolation, enabling ECU consolidation and bandwidth reduction.

Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs

Radiation-tolerant computing is of great importance to the aerospace community because future missions demand more computational power. Of special interest to the aerospace community are flight computers implemented on static random-access-memory-based field-programmable gate arrays. Such computer systems allow the in-flight reconfiguration of hardware that enables the practical deployment of truly reconfigurable computers. However, commercial static random-access-memory-based field-programmable gate arrays are uniquely susceptible to ionizing radiation. This paper introduces a computer architecture for static random-access-memory-based field-programmable gate arrays that resists failures caused by ionizing radiation. The approach extends the widely accepted fault mitigation practice of triple modular redundancy and configuration memory scrubbing by adding spare circuitry and environmental awareness through an ionizing radiation sensor. This paper describes the design of the system in addition to a theore...

Increasing Radiation Tolerance of Field-Programmable- Gate-Array-Based Computers Through Redundancy and Environmental Awareness

SRAM-based FPGAs are highly attractive for space
applications due to their in-flight reconfigurability, decreased
development time and cost, and increased design and testing
flexibility. The Xilinx Virtex-5QV is the first commercially
available Radiation Hardened By Design (RHBD) SRAM-based FPGA;
however, not all of its internal components are hardened against
radiation-induced errors. This thesis examines and quantifies the
additional considerations and techniques designers should employ
with a RHBD SRAM-based FPGA in a space-based processing system to
achieve high operational reliability. Additionally, this work
presents the application of some of these techniques to the
embedded avionics design of the REXIS imaging payload on the
OSIRIS-REx asteroid sample return mission.

Fault tolerant design implementation on radiation hardened by design SRAM-Based FPGAs

This paper presents the design of a many-core computer architecture with fault detection and recovery using partial reconfiguration of an FPGA. The FPGA fabric is partitioned into tiles which contain homogenous soft processors. At any given time, three processors are configured in triple modulo redundancy to detect faults. Spare processors are brought online to replace faulted tiles in real time. A recovery procedure involving partial reconfiguration is used to repair faulted tiles. This type of approach has the advantage of recovering from faults in both the circuit fabric and the configuration RAM of an FPGA in addition to spatially avoiding permanently damaged regions of the chip. 1 2

Spatial avoidance of hardware faults using FPGA partial reconfiguration of tile-based soft processors

This paper presents the design and prototyping of a computing architecture which dynamically reconfigures itself depending on the environment in which it resides. The system switches among three modes of operation (parallel processing, low power, and radiation tolerant) depending on an external radiation sensor and application input from the user. The system was prototyped on a Xilinx Virtex-5 FPGA to verify its feasibility when controlling a series of peripherals under the three modes of operation. This type of system is ideal for robust, real-time applications such as spacecraft control systems.

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Dynamic reconfigurable computing architecture for aerospace applications

Triple Modulo Redundancy (TMR) is one of the most common techniques for fault mitigation in digital systems. TMR-based computing has a natural application to mission critical systems for military and aerospace applications which are exposed to cosmic radiation and are susceptible to Single Event Upsets (SEUs). TMR's increased immunity to SEUs comes at the expense of increased power consumption and area. This paper presents a dynamically selectable TMR architecture which can be used to reduce power consumption when radiation levels are low. We apply this architecture to a test system in order to evaluate its power reduction and area overhead compared to a traditional static TMR approach. We show that the dynamically selectable TMR can be adopted with only a 2.2% increase in equivalent gate count compared to the traditional static TMR when implemented on a Xilinx Virtex-4 FPGA. This approach yields as much as a 67% reduction in power consumption versus a traditional static TMR approach when radiation levels are low.

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Clint Gauer

Papers

Spatial avoidance of hardware faults using FPGA partial reconfiguration of tile-based soft processors

Dynamic reconfigurable computing architecture for aerospace applications

A Power-Efficient Design Approach to Radiation Hardened Digital Circuitry using Dynamically Selectable Triple Modulo Redundancy