Craig L. Keast

TL;DR: In this article, the behavior of top-gated transistors fabricated using carbon, specifically epitaxial graphene on SiC, as the active material was described and the first demonstration and systematic evaluation of arrays of a large number of transistors produced using standard microelectronics methods.

TL;DR: In this paper, the behavior of top gated transistors fabricated using carbon, particularly epitaxial graphene on SiC, as the active material is described, and the first demonstration and systematic evaluation of arrays of a large number of transistors entirely produced using standard microelectronics methods is presented.

TL;DR: In this paper, the authors describe the rationale and development of a wafer-scale three-dimensional (3D) integrated circuit technology and the essential elements of the 3D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision waferwafer alignment using an in-house developed alignment system, low-temperature wafer wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances.

TL;DR: In this article, a 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, developed with 3D fabrication in 150 mm wafer technology, is presented.

TL;DR: In this article, the feasibility of stacking SOI circuits to build 3D-ICs with dense vertical interconnects is discussed, and the results are applied to develop higher performance systems.