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Author

Cristian Bocciarelli

Bio: Cristian Bocciarelli is an academic researcher from Sapienza University of Rome. The author has contributed to research in topics: Computer science & Digital biquad filter. The author has co-authored 1 publications.

Papers
More filters
Journal ArticleDOI
TL;DR: In this paper, a linear transconductor topology is proposed, where class-AB behavior based on adaptive biasing is exploited to improve the linear range of the transceiver.
Abstract: In this paper a novel linear transconductor topology is proposed, where class-AB behavior based on adaptive biasing is exploited to improve the linear range. The adaptive biasing circuit is based on the Winner-Take-All topology already used for class-AB OTAs, and optimized to improve the linearity, and the proposed transconductor features a gain control input for tunability. The transconductor provides a gain of 43 μS while consuming 70 μW. The linear range (1% variation of the dc transconductance gain) is 470 mVpp, about 4.5 times larger than for the corresponding class-A cell. Total harmonic distortion is improved by about 15 dB, and good results in terms of linearity and noise are reported with respect to the state-of-the-art. Simulations of a Gm-C biquad filter based on the proposed transconductor are also reported to validate the design.

1 citations

Proceedings ArticleDOI
18 Jun 2023
TL;DR: In this paper , a 0.6 V dynamic biased, body driven Strong Arm latch is presented, which exploits a charge pump based dynamic biasing configuration that boosts the effective supply headroom.
Abstract: In this paper a novel 0.6 V dynamic biased, body driven Strong Arm latch is presented. The proposed topology exploits a charge pump based dynamic biasing configuration that boosts the effective supply headroom. In addition, the body terminals are used to drive the input pair while the gates are driven by the clock signal to allow for the removal of the tail transistor, resulting in larger peak currents and smaller parasitic capacitances. This reduces power consumption and delay. Moreover, the body driven approach enables rail-to-rail input common mode range (ICMR). As a result, the proposed topology is capable of high-speed operation (up to 2.5 GHz) despite the low supply voltage. At 2.5 GHz the comparator shows a competitive energy-delay product (EDP) of 2.98 fJ/GHz.
Proceedings ArticleDOI
18 Jun 2023
TL;DR: In this article , the authors compared three different forward body biasing schemes: clocked FBB (CFBB), an improvement of CFBB and a new hybrid approach that achieves the best performance in terms of delay.
Abstract: Forward body biasing (FBB) is among the simplest and most effective techniques that can be leveraged to improve the performance of dynamic comparators, as previous works have demonstrated. However, none of these works puts emphasis on comparing different FBB schemes and their robustness against large differential input swings. This is especially important when considering circuits that operate at supply voltages above 0.5 V, where several approaches can be adopted for biasing the substrates without causing the body-source junctions to turn on. This paper compares three different techniques: the clocked FBB (CFBB) proposed in [1], an improvement of CFBB and a new hybrid approach that achieves the best performance in terms of delay. For the sake of brevity, the scope of our experiments has been limited to the Strong Arm latch. All simulations were carried out in a 55 nm CMOS technology at 1 V supply and 2.4 GHz clock frequency.
Journal ArticleDOI
TL;DR: In this paper , an evolution of the Sallen-key biquad architecture is presented, suitable for applications at very high frequency, where the pole of the buffer amplifier is exploited as one of the poles of the biquads, therefore overcoming the constraints it poses on the maximum resonance frequency that can be achieved.
Abstract: In this paper, an evolution of the Sallen–Key biquad architecture is presented, suitable for applications at very high frequency. The pole of the buffer amplifier is exploited as one of the poles of the biquad, therefore overcoming the constraints it poses on the maximum resonance frequency that can be achieved. This allows designing low-pass filters with cutoff frequencies above 10 GHz without using bulky inductors and with good linearity performance provided by the use of feedback. This approach has been exploited to design a biquad in a commercial SiGe BiCMOS technology with maximum f T $$ {f}_T $$ of about 320 GHz. The biquad has been designed to provide a resonance frequency f 0 $$ {f}_0 $$ of 12 GHz and a quality factor Q of 1.9; postlayout simulations show a cutoff frequency in excess of 17 GHz, 15.75 mW of power consumption, an equivalent input noise below 1 μ $$ \upmu $$ Vrms, and −52 dB of total harmonic distortion (THD) for a 640 mVpp input signal, with a very limited area consumption.

Cited by
More filters
Journal ArticleDOI
TL;DR: In this paper , the transconductor-capacitor is rewired such that their input differential voltage lies within the linear regime. And the proposed filter implementation occupies 0.0164 mm and consumes 167μW for the cutoff frequency of 1-MHz.
Abstract: A simple yet effective approach to improve the linearity of the transconductor-capacitor ( Gm-C ) filters is proposed without any area or power overhead. Following a generalized nodal analysis, the transconductors of classical filter topology are rewired such that their input differential voltage lies within the linear regime. The effectiveness of the proposed method is validated through the design and simulation of a fifth-order Butterworth low-pass filter (LPF) in a standard 65-nm CMOS process. The proposed filter implementation occupies 0.0164 mm 2 (0.003 mm 2 /pole) die area and consumes 167-μW for the cut-off frequency of 1-MHz. Operating at 1-V voltage supply, it shows an in-band total harmonic distortion (THD) of –49.14 dB for 200-mV peak-to-peak 1MHz differential voltage. An in-band 3rd-order intercept point (IIP3) of 9.36 dBm is also achieved with an in-band spurious-free-dynamic range (SFDR) greater than 53-dB, all of which reflect meaningful improvements relative to the classical architecture and despite the modest linearity performance of the internal Gm stages.