Cristinel Ababei

Bio: Cristinel Ababei is an academic researcher from Marquette University. The author has contributed to research in topics: Network on a chip & Field-programmable gate array. The author has an hindex of 19, co-authored 81 publications receiving 1313 citations. Previous affiliations of Cristinel Ababei include North Dakota State University & University of Minnesota.

Placement and routing in 3D integrated circuits

Abstract: Three-dimension technologies offer great promise in providing improvements in the overall circuit performance. Physical design plays a major role in the ability to exploit the flexibilities offered in the third dimension, and this article gives an overview of placement and routing methods for FPGA- and ASIC-style designs. We describe CAD techniques for placement and routing in 3D ICs, developed under our 3D analysis and design optimization framework. These approaches address a dichotomy of design styles, both FPGA and ASIC. The factors that are important in each style are different, so that a one-size-fits-all approach is impractical, and therefore, we present separate approaches for 3D physical design for each of these technologies. Hence, our FPGA placement method uses a two-step optimization process that minimizes inter-tier vias first, followed by further optimization within and across tiers. In contrast, the ASIC flow uses cost function weighting to discourage, but not minimize, inter-tier crossings.

Fast timing-driven partitioning-based placement for island style FPGAs

Abstract: In this paper we propose a partitioning-based algorithm for FPGAs The method incorporates simple, but effective heuristics that target delay minimization The placement engine incorporates delay estimations obtained from previously placed and routed circuits using VPR according to V Betz and J Rose (1997) As a result, the delay predictions during placement more accurately resemble those observed after detailed routing, which in turn leads to better delay optimization An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase Simulation results show that the proposed technique can achieve comparable circuit delays (after routing) to those obtained with VPR while achieving a 7-fold speedup in placement runtime

Achieving network on chip fault tolerance by adaptive remapping

Abstract: This paper investigates achieving fault tolerance by adaptive remapping in the context of Networks on Chip. The problem of dynamic application remapping is formulated and an efficient algorithm is proposed to address single and multiple PE failures. The new algorithm can be used to dynamically react and recover from PE failures in order to maintain system functionality. The quality of results is similar to that achieved using simulated annealing but in significantly shorter runtimes.

Efficient Network Reconfiguration Using Minimum Cost Maximum Flow-Based Branch Exchanges and Random Walks-Based Loss Estimations

Abstract: The efficiency of network reconfiguration depends on both the efficiency of the loss estimation technique and the efficiency of the reconfiguration approach itself. We propose two novel algorithmic techniques for speeding-up the computational runtime of both problems. First, we propose an efficient heuristic algorithm to solve the distribution network reconfiguration problem for loss reduction. We formulate the problem of finding incremental branch exchanges as a minimum cost maximum flow problem. This approach finds the best set of concurrent branch exchanges yielding larger loss reduction with fewer iterations, hence significantly reducing the computational runtime. Second, we propose an efficient random walks-based technique for the loss estimation in radial distribution systems. The novelty of this approach lies in its property of localizing the computation. Therefore, bus voltage magnitude updates can be calculated in much shorter computational runtimes in scenarios where the distribution system undergoes isolated topological changes, such as in the case of network reconfiguration. Experiments on distribution systems with sizes of up to 10476 buses demonstrate that the proposed techniques can achieve computational runtimes shorter with up to 7.78 times and with similar or better loss reduction compared to the Baran's reconfiguration technique .

Three-dimensional place and route for FPGAs

Abstract: We present timing-driven partitioning and simulated-annealing (SA)-based placement algorithms together with a detailed routing tool for three-dimensional (3-D) field-programmable gate array (FPGA) integration. The circuit is first divided into layers with a limited number of interlayer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits, in terms of delay and wire length (WL), that 3-D technologies can offer for FPGA fabrics. Experimental results show, on average, a total decrease of 25% in WL and 35% in delay can be achieved over traditional two-dimensional chips, when ten layers are used in 3-D integration

[서평]「Computer Organization and Design, The Hardware/Software Interface」

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Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Abstract: The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field. · Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes · Views of FPGA programming beyond Verilog/VHDL · Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways