D.A. Badillo

Bio: D.A. Badillo is an academic researcher from Motorola. The author has contributed to research in topics: CMOS & Phase noise. The author has an hindex of 4, co-authored 4 publications receiving 79 citations.

Comparison of contemporary CMOS ring oscillators

Abstract: This work presents measured data and analysis, accurately comparing three, four-stage ring oscillators. The delay cell topologies considered here include the linear source coupled, and two saturating types. Each oscillator is fabricated concurrently in a 1.8 V, 0.18 /spl mu/m CMOS process and is characterized for phase noise, power consumption and tuning range.

1.5V CMOS current reference with extended temperature operating range

Abstract: Traditional bandgap based current references have restricted temperature operating range due to the limited input common mode range of the feedback amplifier. This paper introduces a modified bandgap current reference that overcomes this limitation by placing a natural device (V/sub th/ /spl sim/ 0V) level shift stage between the amplifier and the bandgap. The circuit has been fabricated in a 0.25-/spl mu/m CMOS process. It generates a reference current of 5/spl mu/A with a temperature variation of 7% over an extended temperature range of -40/spl deg/C to 150/spl deg/C. The bandgap occupies approximately 170/spl times/80/spl mu/m/sup 2/ and draws 56/spl mu/A from a 1.5V supply.

A low phase noise 2.0 V 900 MHz CMOS voltage controlled ring oscillator

Abstract: A CMOS voltage controlled ring oscillator with quadrature output is presented. The circuit is designed in a 0.18 /spl mu/m CMOS process and operates on a 2.0 V supply. The VCO has a tuning range of 650 MHz to 1.04 GHz. At 913 MHz the VCO has a phase noise of -116.55 dBc/Hz at a frequency offset of 600 KHz. The average power consumed at 913 MHz is 18.95 mW.

A novel low phase noise 1.8V 900MHz CMOS voltage controlled ring oscillator

Abstract: A 900MHz CMOS voltage controlled ring oscillator with quadrature output is presented. The circuit is designed in a 0.18/spl mu/m CMOS process and operates on a 1.8V supply. The VCO has a tuning range of 475MHz to 1.0GHz. At 900MHz the VCO has a phase noise of -109dBc/Hz at a frequency offset of 600kHz. The average power consumed at 900MHz is 19.2mW.

Phase Noise and Jitter in CMOS Ring Oscillators

Abstract: A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator

A 1-V CMOS Current Reference With Temperature and Process Compensation

Abstract: A 1-V current reference fabricated in a standard CMOS process is described. Temperature compensation is achieved from a bandgap reference core using a transimpedance amplifier in order to generate an intermediate voltage reference, VREF. This voltage applied to the gate of a carefully sized nMOS output transistor provides a reference drain current, IREF , nearly independent of temperature by mutual compensation of mobility and threshold voltage variations. The circuit topology allows for compensation of threshold voltage variation due to process parameters as well. The current reference has been fabricated in a standard 0.18-mum CMOS process. Results from nineteen samples measured over a temperature range of 0degC to 100degC , showed values of IREF of 144.3 muA plusmn 7% and VREF of 610.9 mV plusmn 2% due to the combined effect of temperature and process variations.

Delta–Sigma A/D Conversion Via Time-Mode Signal Processing

Abstract: In this paper, a signal processing methodology is proposed that performs delta-sigma (DeltaSigma) analog-to-digital (A/D) conversion on voltage signals while implementing all the circuits in a digital CMOS logic style. This methodology, called time-mode (TM) signal processing, uses time-difference variables as an intermediate signal between the input voltage and the digital output. The resulting low-cost silicon devices offer very compact, low-power, high-speed, and robust A/D converter (ADC) alternatives. A first-order DeltaSigma ADC is implemented using this methodology. Two ICs were fabricated in a 0.18- mum CMOS technology to demonstrate the feasibility of the TM DeltaSigma ADC approach. The first IC implements a single-ended input design while a differential design was fabricated in the second IC. Experimental results reveal that these devices can achieve 7-9-bit resolutions within 125-400-kHz bandwidths, while occupying areas smaller than 50 mum t50 mum and consuming less than 800 muW.

A Fully-Integrated, Short-Range, Low Data Rate FM-UWB Transmitter in 90 nm CMOS

Abstract: This paper presents a fully-integrated 3-5 GHz-band FM-UWB transmitter implemented in 90 nm bulk CMOS. The front-end consists of an RF current-controlled oscillator (RF-ICO) and class-AB power amplifier. Transmit data modulates a sub-carrier oscillator. The 2-FSK modulated output is amplified by a transconductor, and directly modulates the RF-ICO tune input. A successive approximation register (SAR) algorithm and on-chip all-digital frequency-locked loop (FLL) calibrate the carrier and sub-carrier frequencies. All voltage and current references required by the transmitter are included on-chip. The 0.2 × 0.5 mm2 active area transmitter consumes 900 μW from a 1 V supply. Energy efficiency of the transmitter is 9 nJ/bit running continuously at 100 kbits/s.

Comparison of contemporary CMOS ring oscillators

Abstract: This work presents measured data and analysis, accurately comparing three, four-stage ring oscillators. The delay cell topologies considered here include the linear source coupled, and two saturating types. Each oscillator is fabricated concurrently in a 1.8 V, 0.18 /spl mu/m CMOS process and is characterized for phase noise, power consumption and tuning range.