The objective of this paper is to outline a methodology for the computation of the response of a multiconductor transmission line terminated by linear networks. The lines are embedded in a multilayered lossy dielectric media and have arbitrary cross sections, but uniform along the length. To check the accuracy of the theoretical results, extensive experimental verification has been carried out.

Analysis of Multiconductor Transmission Lines

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale.

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Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

Evaluation of the time-domain response of multiconductor transmission lines is of great importance in the analysis of the crosstalk in fast digital circuit interconnections, as well as in the analysis of power lines. Several techniques for the computation of the line response, starting from the known circuit-theory parameters, are presented and evaluated. These methods are: time-stepping solution of the telegrapher equations, modal analysis in the time domain, model analysis in the frequency domain, and a convolution technique which uses line Green's functions. The last method can treat the most general case of lossy transmission lines with nonlinear terminal networks. Numerical and experimental results are presented to illustrate these techniques and to give insight into the crosstalk problems in fast digital circuits.

Time-Domain Response of Multiconductor Transmission Lines

A closed-form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful criterion. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC II circuit based on a 0.25-/spl mu/m IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this paper is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect.

Figures of merit to characterize the importance of on-chip inductance

Closed-form solutions for the 50% delay, rise time, overshoots, and settling time of signals in an RLC tree are presented. These solutions have the same accuracy characteristics of the Elmore delay for RC trees and preserves the simplicity and recursive characteristics of the Elmore delay. Specifically, the complexity of calculating the time domain responses at all the nodes of an RLC tree is linearly proportional to the number of branches in the tree and the solutions are always stable. The closed-form expressions introduced here consider all damping conditions of an RLC circuit including the underdamped response, which is not considered by the Elmore delay due to the nonmonotone nature of the response. The continuous analytical nature of the solutions makes these expressions suitable for design methodologies and optimization techniques. Also, the solutions have significantly improved accuracy as compared to the Elmore delay for an overdamped response. The solutions introduced here for RLC trees can be practically used for the same purposes that the Elmore delay is used for RC trees.

Equivalent Elmore delay for RLC trees

By way of worked examples in typical but somewhat idealized cases the effect on circuit speed of circuit interconnections is studied. The source, calculation and minimization of interconnection crosstalk is also discussed. It is shown that high-speed circuitry must be miniaturized and the implications are discussed.

D. B. Jarvis

Papers

The Effects of Interconnections on High-Speed Logic Circuits