D.B.M. Klaasen

Bio: D.B.M. Klaasen is an academic researcher. The author has contributed to research in topics: AND gate & Flicker noise. The author has an hindex of 1, co-authored 1 publications receiving 33 citations.

Compact modeling of drain and gate current noise for RF CMOS

Abstract: A model for RF CMOS circuit design is presented that is capable of predicting drain and gate current noise without adjusting any parameters. Additionally, the presence of (i) noise associated with avalanche multiplication, and (ii) shot noise of the direct-tunneling gate current in leaky dielectrics is revealed.

SP: an advanced surface-potential-based compact MOSFET model

Abstract: This work describes an advanced physics-based compact MOSFET model (SP). Both the quasistatic and nonquasi-static versions of SP are surface-potential-based. The model is symmetric, includes the accumulation region, small-geometry effects, and has a consistent current and charge formulation. The surface potential is computed analytically and there are no iterative loops anywhere in the model. Availability of the surface potential in the source-drain overlap regions enables a physics-based formulation of the extrinsic model (e.g., gate tunneling current) and allows for a noise model free of discontinuities or unphysical interpolation schemes. Simulation results are used to illustrate the interplay between the model structure and circuit design.

SP: An Advanced Surface-Potential-Based Compact MOSFET Model (invited)

Abstract: This work describes an advanced physics-based compact MOSFET model (SP). Both the quasi-static and non-quasistatic versions of SP are surface-potential-based. The model is symmetric, includes the accumulation region, small-geometry effects, and has a consistent current and charge formulation. The surface potential is computed analytically and there are no iterative loops anywhere in the model. Availability of the surface potential in the source-drain overlap regions enables a physics-based formulation of the extrinsic model (e.g. gate tunneling current) and allows for a noise model free of discontinuities or unphysical interpolation schemes. Simulation results are used to illustrate the interplay between the model structure and circuit design.

Improved Y-factor method for wide-band on-wafer noise-parameter measurements

Abstract: A new noise-figure measurement method, which combines the simplicity of the "classical" Y-factor method with the accuracy of the widely used "cold noise-source" method, is reported. Implemented in our fully automated wide-band 1-18-GHz on-wafer noise-parameter measurement system, accurate results are obtained using a small set of precharacterized source impedances. We illustrate our method and its accuracy with data taken on a low-noise GaAs pseudomorphic high electron-mobility transistor device, and quantify the impact of the instrumental uncertainties on the extracted noise parameters.

CMOS LC-oscillator phase-noise analysis using nonlinear models

Abstract: In this paper, a second-order stochastic differential equation is used as a tool for the analysis of phase noise in a submicron CMOS LC oscillator. A cross-coupled topology typical of integrated CMOS designs is considered. Nonlinear limiting and mobility degradation effects in the circuit are modeled and used to predict the statistics of the random amplitude and phase deviations in terms of design variables. Assuming Gaussian noise disturbances and describing the phase noise as a random diffusion process, the average phase-noise power spectrum is derived and its accuracy verified with measurement and simulation results. Calculations for phase noise arising from stationary tank noise, nonstationary channel thermal noise, and flicker noise are discussed. The analysis is used to emphasize the fundamental power/performance tradeoff associated with compensation of tank losses via adjustments in the power supply and device size.