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Author

D. De Ceuster

Other affiliations: Katholieke Universiteit Leuven
Bio: D. De Ceuster is an academic researcher from Université catholique de Louvain. The author has contributed to research in topics: CMOS & Operational amplifier. The author has an hindex of 5, co-authored 7 publications receiving 248 citations. Previous affiliations of D. De Ceuster include Katholieke Universiteit Leuven.

Papers
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Journal ArticleDOI
TL;DR: In this article, design guidelines using two analog parameters (Early voltage and transconductance to drain current ratio) are proposed for correct operation of silicon-on-insulator (SOI) CMOS operational amplifiers (opamp) at elevated temperature up to 300/spl deg/C.
Abstract: Design guidelines using two analog parameters (Early voltage and transconductance to drain current ratio) are proposed for correct operation of silicon-on-insulator (SOI) CMOS operational amplifiers (opamp) at elevated temperature up to 300/spl deg/C The dependence of these parameters on temperature is first described A new single-stage CMOS opamp model using only these two parameters is presented and compared to measurements of several implementations operating up to 300/spl deg/C for applications such as micropower (below 4 /spl mu/W at 12 V supply voltage), high gain (65 dB) or high frequency up to 100 MHz Trade-offs among such factors as gain, bandwidth, phase margin, signal swing, noise, matching, slew rate and power consumption are described The extension to other architectures is suggested and the design methodology is valid for bulk as well as SOI CMOS opamps

112 citations

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate that FD SOI MOSFETs exhibit near-ideal body factor, sub-threshold slope and current drive properties for mixed fabrication and operation under low supply voltage of analog, digital and microwave components.
Abstract: This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis.

83 citations

Journal ArticleDOI
TL;DR: In this paper, the performance of micropower single-stage CMOS OTAs implemented in SOI or bulk technologies is compared and the improvements resulting from the superior device characteristics of fully-depleted SOI MOSFETs are discussed.
Abstract: The performances of micropower single-stage CMOS OTAs implemented in SOI or bulk technologies are compared. The improvements resulting from the superior device characteristics of fully-depleted SOI MOSFETs are discussed. Experimental verifications support the theoretical predictions.

41 citations

Journal ArticleDOI
TL;DR: In this paper, a recessed LOCOS technique instead of a standard LOCOS process was proposed to eliminate parasitic edge transistor leakage in thin-film SOI MOSFETs.
Abstract: The authors propose the use of a recessed LOCOS technique instead of a standard LOCOS process to eliminate parasitic edge transistor leakage in thin-film SOI MOSFETs. This technique helps to increase the sidewall threshold voltage by both avoiding excess boron segregation into the field oxide, and providing a smoother edge rounding than that obtained by a classical LOCOS process.

12 citations

Journal ArticleDOI
TL;DR: In this article, the serial-parallel association of SOI MOSFETs proves to be useful for increasing the breakdown voltage and the early voltage of transistor structures, allowing one to realize current mirrors with an output-to-input current ratio close to unity in the weak, moderate and strong inversion regimes of the MOS FETs.
Abstract: The serial-parallel association of SOI MOSFETs proves to be useful for increasing the breakdown voltage and the early voltage of transistor structures. This permits one to realise current mirrors with an output-to-input current ratio close to unity in the weak, moderate and strong inversion regimes of the MOSFETs.

12 citations


Cited by
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Journal ArticleDOI
TL;DR: In this paper, a new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used.
Abstract: A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g/sub m//I/sub D/ and the normalized current I/sub D//(W/L). The g/sub m//I/sub D/ indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).

604 citations

Patent
10 Oct 2002
TL;DR: In this paper, a fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements, which includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.
Abstract: An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

240 citations

Patent
11 Jul 2006
TL;DR: In this article, a method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) was described, which can be adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFs, thereby yielding improvements in FET performance.
Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

175 citations

Journal ArticleDOI
10 Jul 2006
TL;DR: The feasibility of a complete, cubic millimeter scale, single-chip sensor node is explored by examining practical limits on process integration and energetic cost of short-range RF communication.
Abstract: Wireless sensor nodes are autonomous devices incorporating sensing, power, computation, and communication into one system. Applications for large scale networks of these nodes are presented in the context of their impact on the hardware design. The demand for low unit cost and multiyear lifetimes, combined with progress in CMOS and MEMS processing, are driving development of SoC solutions for sensor nodes at the cubic centimeter scale with a minimum number of off-chip components. Here, the feasibility of a complete, cubic millimeter scale, single-chip sensor node is explored by examining practical limits on process integration and energetic cost of short-range RF communication. Autonomous cubic millimeter nodes appear within reach, but process complexity and substantial sacrifices in performance involved with a true single-chip solution establish a tradeoff between integration and assembly.

174 citations

Patent
02 Mar 2009
TL;DR: In this paper, a method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described, which facilitates digitally controlling capacitance applied between a first and second terminal.
Abstract: A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

172 citations