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Author

D.H. Horrocks

Bio: D.H. Horrocks is an academic researcher from Cardiff University. The author has contributed to research in topics: Digital filter & Infinite impulse response. The author has an hindex of 4, co-authored 7 publications receiving 347 citations.

Papers
More filters
Journal ArticleDOI
01 Jun 1991
TL;DR: Vertex rearrangement, retiming and edge elimination techniques are presented which facilitate the generation of a logical graph with an efficient allocation of pipeline registers.
Abstract: The authors outline a design methodology for the realisation of digital filtering structures with significantly reduced numbers of elementary arithmetic operations. The directed acyclic graphs which result from the design algorithms completely describe the filter arithmetically and may be mapped directly onto hardware or software realisations. Vertex rearrangement, retiming and edge elimination techniques are presented which facilitate the generation of a logical graph with an efficient allocation of pipeline registers. An example of the technique is given for a bit-serial realisation employing a bit-level pipeline. >

306 citations

Proceedings ArticleDOI
07 Jun 1988
TL;DR: These methods are extended by the authors to permit the inclusion of edges with gains which may assume any power of two, which facilitates a tradeoff between addition or subtraction and shift operations which can be beneficial in many implementations.
Abstract: A graph-based synthesis technique has been developed which allows digital filters to be realized with significantly reduced numbers of primitive arithmetic operations. Previously presented work has relied on the use of unity-gain graph edges. These methods are extended by the authors to permit the inclusion of edges with gains which may assume any power of two. This facilitates a tradeoff between addition or subtraction and shift operations which can be beneficial in many implementations. For VLSI implementations especially, judicious placement of processing elements, routing, and allocation of pipeline registers, make for an efficient filter implementation. >

17 citations

Journal ArticleDOI
TL;DR: The letter presents a class of algorithms which generate filtering structures with reduced numbers of elementary operations and the directed acyclic graphs which result completely describe the device structure, and may be mapped directly into hardware or software realisations.
Abstract: The letter presents a class of algorithms which generate filtering structures with reduced numbers of elementary operations. The directed acyclic graphs which result completely describe the device structure, and may be mapped directly into hardware or software realisations.

14 citations

Proceedings ArticleDOI
03 May 1993
TL;DR: Results are presented for a range of elliptic filters with varying wordlength and order, realized using direct form, parallel and cascade structures, showing significant savings when compared with the equivalent canonical signed digit multiplier coding scheme.
Abstract: Realization techniques for infinite impulse response (IIR) digital filters based on the primitive operator graph synthesis method are presented. The approach exploits the redundancy present in the filter multiplier structure when the coefficients are invariant, allowing partial result reuse throughout the filter structure. Results are presented for a range of elliptic filters with varying wordlength and order, realized using direct form, parallel and cascade structures. These show significant savings when compared with the equivalent canonical signed digit multiplier coding scheme. >

10 citations

Proceedings ArticleDOI
23 May 1989
TL;DR: Response error estimates are derived for direct-form FIR (finite impulse response) digital filters having low-pass, high- pass, and bandpass characteristics.
Abstract: Response error estimates are derived for direct-form FIR (finite impulse response) digital filters having low-pass, high-pass, and bandpass characteristics. Simple-to-apply formulas are obtained on the basis of two observations: first, that the discontinuous relationships between a floating can be replaced by a continuous approximation; and secondly, that in the classes of filter considered, the impulse response possesses a closed form. Formulas that show the effect of wordlength, filter order, and filter bandwidth are derived. Simulation studies that confirm these estimates are reported. >

3 citations


Cited by
More filters
Journal ArticleDOI
TL;DR: Three new algorithms for the design of multiplier blocks are described: an efficient modification to an existing algorithm, a new algorithm giving better results, and a hybrid of these two which trades off performance against computation time.
Abstract: The computational complexity of VLSI digital filters using fixed point binary multiplier coefficients is normally dominated by the number of adders used in the implementation of the multipliers. It has been shown that using multiplier blocks to exploit redundancy across the coefficients results in significant reductions in complexity over methods using canonic signed-digit (CSD) representation, which in turn are less complex than standard binary representation. Three new algorithms for the design of multiplier blocks are described: an efficient modification to an existing algorithm, a new algorithm giving better results, and a hybrid of these two which trades off performance against computation time. Significant savings in filter implementation cost over existing techniques result in all three cases. For a given wordlength, it was found that a threshold set size exists above which the multiplier block is extremely likely to be optimal. In this region, design computation time is substantially reduced. >

601 citations

Journal ArticleDOI
TL;DR: This paper examines methods for optimizing the design of CSD multipliers, and in particular the gains that can be made by sharing subexpressions, and it is shown that sharing the two most common sub expressions can be expected to lead to a 33% saving of the number of additions.
Abstract: A common way of implementing constant multiplication is by a series of shift and add operations. As is well known, if the multiplier is represented in Canonical Signed Digit (CSD) form, then the number of additions (or subtractions) used will be a minimum. This paper examines methods for optimizing the design of CSD multipliers, and in particular the gains that can be made by sharing subexpressions. In the case where several multipliers are present in a network of operators, for instance in an FIR filter, the savings achieved by identifying common subexpressions can be as much as 50% of the total number of operators. The asymptotic frequency of the most common subexpression is analyzed mathematically, and it is shown that sharing the two most common subexpressions can be expected to lead to a 33% saving of the number of additions.

597 citations

Journal ArticleDOI
TL;DR: This work proposes a new algorithm for the multiple constant multiplication problem, which produces solutions that require up to 20% less additions and subtractions than the best previously known algorithm and can handle problem sizes as large as 100 32-bit constants in a time acceptable for most applications.
Abstract: A variable can be multiplied by a given set of fixed-point constants using a multiplier block that consists exclusively of additions, subtractions, and shifts. The generation of a multiplier block from the set of constants is known as the multiple constant multiplication (MCM) problem. Finding the optimal solution, namely, the one with the fewest number of additions and subtractions, is known to be NP-complete. We propose a new algorithm for the MCM problem, which produces solutions that require up to 20p less additions and subtractions than the best previously known algorithm. At the same time our algorithm, in contrast to the closest competing algorithm, is not limited by the constant bitwidths. We present our algorithm using a unifying formal framework for the best, graph-based MCM algorithms and provide a detailed runtime analysis and experimental evaluation. We show that our algorithm can handle problem sizes as large as 100 32-bit constants in a time acceptable for most applications. The implementation of the new algorithm is available at www.spiral.net.

421 citations

Journal ArticleDOI
01 Jun 1991
TL;DR: Vertex rearrangement, retiming and edge elimination techniques are presented which facilitate the generation of a logical graph with an efficient allocation of pipeline registers.
Abstract: The authors outline a design methodology for the realisation of digital filtering structures with significantly reduced numbers of elementary arithmetic operations. The directed acyclic graphs which result from the design algorithms completely describe the filter arithmetically and may be mapped directly onto hardware or software realisations. Vertex rearrangement, retiming and edge elimination techniques are presented which facilitate the generation of a logical graph with an efficient allocation of pipeline registers. An example of the technique is given for a bit-serial realisation employing a bit-level pipeline. >

306 citations

Journal ArticleDOI
TL;DR: A new solution of the multiple constant multiplication problem based on the common subexpression elimination technique is presented and it is shown that the number of add/subtract operations can be reduced significantly this way.
Abstract: The problem of an efficient hardware implementation of multiplications with one or more constants is encountered in many different digital signal-processing areas, such as image processing or digital filter optimization. In a more general form, this is a problem of common subexpression elimination, and as such it also occurs in compiler optimization and many high-level synthesis tasks. An efficient solution of this problem can yield significant improvements in important design parameters like implementation area or power consumption. In this paper, a new solution of the multiple constant multiplication problem based on the common subexpression elimination technique is presented. The performance of our method is demonstrated primarily on a finite-duration impulse response filter design. The idea is to implement a set of constant multiplications as a set of add-shift operations and to optimize these with respect to the common subexpressions afterwards. We show that the number of add/subtract operations can be reduced significantly this way. The applicability of the presented algorithm to the different high-level synthesis tasks is also indicated. Benchmarks demonstrating the algorithm's efficiency are included as well.

297 citations