Due to the rapid development of IC technology the traditional packaging concepts are making a transition into more complex system integration techniques in order to enable the constantly increasing demand for more functionality, performance, miniaturisation and lower cost. These new packaging concepts (as e.g. system in package, 3D integration, MEMS-devices) will have to combine smaller structures and layers made of new materials with even higher reliability. As these structures will more and more display nano-features, a coupled experimental and simulative approach has to account for this development to assure design for reliability in the future. A necessary “nano-reliability” approach as a scientific discipline has to encompass research on the properties and failure behaviour of materials and material interfaces under explicit consideration of their micro- and nano-structure and the effects hereby induced. It uses micro- and nano-analytical methods in simulation and experiment to consistently describe failure mechanisms over these length scales for more accurate and physically motivated lifetime prediction models. This paper deals with the thermo-mechanical reliability of microelectronic components and systems and methods to analyse and predict it. Various methods are presented to enable lifetime prediction on system, component and material level, the latter promoting the field of nano-reliability for future packaging challenges in advanced electronics system integration.

Lifetime modelling for microsystems integration: from nano to systems

In this paper we examine the thermo-mechanical reliability of polymer-encapsulated chip-on-board (COB) assemblies for power applications by simulation and experiment. Thereby the focus is set on the low cycle fatigue failure behaviour of the die-attach material under thermal cycling conditions. As die-attach material different solder materials and Ag-filled thermal adhesives have been used. The encapsulation was performed with a soft silicone-based and hard silica-reinforced epoxy-based material, respectively. An other process variable takes into account die-tilt. The study was carried out as a feasibility analysis in the course of a COB technology development. To this end lifetime models have been employed to correlate crack growth in the, i.e. attach to a computational accumulative failure criterion which allows to consistently describe ad predict quantitatively the lifetime of the assemblies. Thereby a considerable influence of the encapsulation was found. In particular it could be shown that a hard encapsulation largely increases reliability for solder die-attach.

Thermo-mechanical reliability during technology development of power chip-on-board assemblies with encapsulation

Trends of power semiconductor wafer level packaging

The amount of heat to be dissipated from power electronics and microprocessors increases more and more. Therefore new interface materials with high electrical and thermal conductivity have to be considered. Silver is one of a few materials which can fulfil these demands. New low temperature, low pressure Ag-Sinter technologies allow it to use Silver as die attach material instead of solder or glue. Even though silver has excellent thermal and electrical properties, thermo-mechanical reliability aspects have to be considered. In this paper the thermo-mechanical reliability of chip-on-board (COB) assemblies for power applications are studied by experiment and simulation. Thereby the main focus is set on the characterization methods and low cycle fatigue failure behaviour of the die-attach material under thermal cycling conditions. Part of the work has been accomplished within the running EU Project “Nanopack”.

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Reliability Analysis of Low Temperature Low Pressure Ag-Sinter Die Attach

As the demand for new thermal technologies and materials has been increasing over the years to provide thermal solutions to the next generation of power electronics, microprocessors and high-power optical systems also thermal characterisation methods have to keep up with the pace of this development with respect to resolution and accuracy. We have developed both bulk and interface technologies to reduce thermal resistance using Ag and Au-based materials and low-T and low-p processes to render them eligible for the electronics industry. New processes to generate nano-enhanced surface structures as well as thermo-compression bonding are examined within this paper. Along with these processes especially designed test stands are described which are able to extract the effects achieved by the technological advances.

Advances in thermal interface technology: mono-metal interconnect formation, processing and characterisation

A review of recent advances in power electronic packaging is presented based on the development of power device integration. The presentation will cover in more detail how advances in both semiconductor content and power advanced package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, the role of modeling is key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.

D. Kinzer

Papers

Trends of Power Electronic Packaging and Modeling