Afully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large-and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ inv is controlled by the voltage differenceV P — Vch whereV ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV P is defined as the particular value of Vch, such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV P —V S andV P —V D Using the charge sheet model with the assumption of constant doping in the channel, the drain currentIDis derived and expressed as the difference between a forward componentI F and a reverse componentI R. Each of these is proportional to a function ofV P —V S respectivelyV P —V D through a specific currentI S This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

A unified flicker noise model which incorporates both the number fluctuation and the correlated surface mobility fluctuation mechanism is discussed. The latter is attributed to the Coulombic scattering effect of the fluctuating oxide charge. The model has a functional form resembling that of the number fluctuation theory, but at certain bias conditions it may reduce to a form compatible with Hooge's empirical expression. The model can unify the noise data reported in the literature, without making any ad hoc assumption on the noise generation mechanism. Specifically, the model can predict the right magnitude and bias dependence of the empirical Hooge parameter. Simulated flicker noise characteristics obtained with a circuit-simulation-oriented flicker noise model based on the new formulation were compared with experimental noise data. Excellent agreement between the calculations and measurement was observed in both the linear and saturation regions for MOS transistors fabricated by different technologies. The work shows that the flicker noise in MOS transistors can be completely explained by the trap charge fluctuation mechanism, which produces mobile carrier number fluctuation and correlated surface mobility fluctuation. >

A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors

In emerging embedded applications such as wireless sensor networks, the key metric is minimizing energy dissipation rather than processor speed. Minimum energy analysis of CMOS circuits estimates the optimal operating point of clock frequencies, supply voltage, and threshold voltage according to A. Chandrakasan et al. (see ibid., vol.27, no.4, p.473-84, Apr. 1992). The minimum energy analysis shows that the optimal power supply typically occurs in subthreshold (e.g., supply voltages that are below device thresholds). New subthreshold logic and memory design methodologies are developed and demonstrated on a fast Fourier transform (FFT) processor. The FFT processor uses an energy-aware architecture that allows for variable FFT length (128-1024 point), variable bit-precision (8 b and 16 b) and is designed to investigate the estimated minimum energy point. The FFT processor is fabricated using a standard 0.18-/spl mu/m CMOS logic process and operates down to 180 mV. The minimum energy point for the 16-b 1024-point FFT processor occurs at 350-mV supply voltage where it dissipates 155 nJ/FFT at a clock frequency of 10 kHz.

A 180-mV subthreshold FFT processor using a minimum energy design methodology

A software energy estimation methodology is presented that avoids explicit characterization of instruction energy consumption and pre-dicts energy consumption to within 3% accuracy for a set of bench-mark programs evaluated on the StrongARM SA-1100 and Hitachi SH-4 microprocessors. The tool, JouleTrack, is available as an online resource and has various estimation levels. It also isolates the switch-ing and leakage components of the energy consumption.

/pdf/jouletrack-a-web-based-tool-for-software-energy-profiling-1r5jydydfp.pdf

JouleTrack: a web based tool for software energy profiling

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by IISPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

The Berkeley short-channel IGFET model (BSIM), an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design are described. Both the strong-inversion and weak-inversion components of the drain current expression are included. In order to speed up the circuit-simulation execution time, the dependence of the drain current on the substrate bias has been modeled with a numerical approximation. This approximation also simplifies the transistor terminal-charge expressions. The charge model was derived from its drain-current counterpart to preserve consistency of device physics. Charge conservation is guaranteed in this model.

D.L. Scharfetter

Papers

BSIM: Berkeley short-channel IGFET model for MOS transistors