This paper presents two voltage controlled oscillators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-μm complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of -120 dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance.

Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies

This paper develops a novel design method for synthesizing the multi-passband filter with high flexibility in various passband location and fractional bandwidth. Using the proposed compensation technology in the equivalent circuit of multi-passband resonator, the cutoff frequencies and matching property in passband regions can be improved. Tripleand quad-band bandpass filters operating in both wireless local area network (WLAN) 802.11 a/b/g and worldwide interoperability for microwave access (WiMAX) systems are presented to verify the design method. The lumped-element coplanar waveguide stub fabricated by the split-ring resonator is established to realize filter with compact size. All the measured, full-wave simulated and equivalent-circuit modeled results illustrate a good agreement among them, which validates the multi-passband design methodology and shows the advantages of DC elimination and deep rejection between each passband.

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Synthesis of triple-band and quad-band bandpass filters using lumped-element coplanar waveguide resonators

A dual-band antenna-in-package for millimeter-wave (mmW) applications is presented in the paper. The proposed antenna, which consists of a radiating slot and an air-filled cavity, is fed by a microstrip loaded with two tuning open-circuited stubs through a coupling C-shape aperture to achieve dual-band characteristics. The air-filled cavity, which is formed by the space between CMOS chip and integrated passive device substrate after flip-chip assembly process, can reduce loss and improve antenna gain. Simulation and measurement regarding antenna reflection coefficient, radiation pattern, and peak gain are conducted for design validation. The measured results show that the antenna can operate in V-band and E-band, and the impedance bandwidths with the reflection coefficient less than -10 dB are 6.1% and 5.8%, respectively. The measured gains are -2 dBi at 58 GHz and 0.3 dBi at 77 GHz, respectively. The proposed antenna is well suited for dual-band mmW high-data-rate wireless communication systems.

Design of Dual-Band Millimeter-Wave Antenna-in-Package Using Flip-Chip Assembly

We make suspended inductors and 2.45 GHz BPFs on the selectively anodized aluminum. The thick anodized alumina is used as the supporting dielectric and it is easily removed by using chemical wet-etching. The thickness of anodized alumina is 80 mum and the depth of the total air-cavity is 200 mum. The fabricated inductor over an air cavity has a 25% greater Q factor and 21% higher inductance at 2 GHz compared to an inductor on anodized aluminum. The 2.45 GHz BPF adjusting the suspended inductors has 2.8 dB of insertion loss with a narrow bandwidth.

Suspended Spiral Inductor and Band-Pass Filter on Thick Anodized Aluminum Oxide

A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.

Varying thickness inductor

An integrated passive device (IPD) technology has been developed to meet the ever increasing needs of size and cost reduction in radio front-end transceiver module applications. Electromagnetic (EM) simulation was used extensively in the design of the process technology and the optimization of inductor and harmonic filter designs and layouts. Parameters such as inductor shape, inner diameter, metal thickness, metal width, and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes 1) a thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD SiN dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) a 10 mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulations and electromagnetic (EM) simulations have been used in the harmonic filter circuit designs for high accuracy and fast design cycle time. This paper will present the EM simulation calibration and demonstrate the importance of using EM simulation in the filter design in order to achieve first-time success in wafer fabrication. The fabricated IPD devices have insertion loss of 0.5 dB and harmonic rejections of 30dB with die size of 1.42 mm for high band (1710 MHz-1910 MHz) and 1.89 mm for low band (824-915 MHz) harmonic filters.

Compact Harmonic Filter Design and Fabrication Using IPD Technology

An integrated passive device (IPD) on GaAs technology has been developed to meet the ever increasing needs of size and cost reduction in radio transmit module applications. Extensive electromagnetic (EM) simulations were used in the design of process technology and the optimization of inductor and harmonic filters design and layout. Parameters such as inductor shape, inner diameter, metal thickness, metal width and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes the following features: 1) thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD Si/sub 3/N/sub 4/ dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) 10mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulation and electromagnetic (EM) simulations have been used in the harmonic filter circuit design for fast design cycle time and high accuracy. This paper presents the EM simulation calibration and demonstrate the importance of using EM simulations in filter design in order to achieve success in first wafer fabrication. The fabricated IPD devices have insertion loss of 30dB with die size of 1.42mm/sup 2/ for high band (1710MHz -1910MHz) and 1.89mm/sup 2/ for low band (824MHz-915MHz) harmonic filters.

D. Maurer

Papers

Compact Harmonic Filter Design and Fabrication Using IPD Technology

Compact harmonic filter design and fabrication using IPD technology