D. Nee

Bio: D. Nee is an academic researcher from STMicroelectronics. The author has contributed to research in topics: EEPROM & EPROM. The author has an hindex of 5, co-authored 18 publications receiving 198 citations.

EEPROM memory: threshold voltage built in self diagnosis

Abstract: Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a build in structure to extract this information is a very relevant choice to fast diagnose failure in the memory. Thus, the objective of this paper is to present a built in self-diagnosis of EEPROM memory cells, based on threshold voltage extraction. In order to extract the threshold voltage, the modified circuit and the associated test sequence are presented. Based on the threshold voltage extraction, complementary information is proposed to improve the classical memory diagnosis

EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement

Abstract: Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a built in structure to extract this information is a very relevant choice to fast diagnose the failure in the memory. Thus, the objective of this paper is to present a built in self-diagnosis of EEPROM memory cells, based on threshold voltage extraction. In order to extract the threshold voltage, the modified circuit and the associated test sequence are presented. Based on the threshold voltage extraction, complementary information is proposed to improve the classical memory diagnosis methodology.

Floating-gate EEPROM cell model based on MOS model 9

Abstract: The objective of this paper is to present an electrically erasable programmable read only memory cell model for static and transient simulations. As a core element of this model, a MM9 model has been used coupled with the charges' neutrality expression in the structure. The charges' neutrality, including the charges trapped on the floating gate, is applied to determine the potential on the floating gate. From the floating gate potential, related to the terminal voltages, the drain current and the different charges present in the cell structure are calculated with the MM9 formulation. Moreover, this pragmatic model takes into account the geometric dependences of the cell. This model has been successfully implemented in Eldo.

EEPROM Compact Model with SILC Simulation Capability

Abstract: The objective of this paper is to present a EEPROM compact model suitable for SILC simulation. The SILC module allows simulating the retention capability of the cell after stress. Test chip array distribution and standard tunnel capacitor are used to extract the SILC module parameters. Thus the extraction procedure is detailed. The description of the complete model is presented. A simulation example is given and validated versus measurements.

Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells

Abstract: A method for decoding a plurality of flash memory cells which are error-correction-coded as a unit, the method comprising providing a hard-decoding success indication indicating whether or not hard-decoding is at least likely to be successful; and soft-decoding the plurality of flash memory cells at a first resolution only if the hard-decoding success indication indicates that the hard-decoding is not at least likely to be successful.

Measuring threshold voltage distribution in memory using an aggregate characteristic

Abstract: A threshold voltage distribution of a set of storage elements in a memory device is measured by sweeping a control gate voltage while measuring a characteristic of the set of storage elements as a whole (710). The characteristic indicates how many of the storage elements meet a given condition, such as being in a conductive state. For example, the characteristic may be a combined current, voltage or capacitance of the set which is measured at a common source of the set. The control gate voltage can be generated internally within a memory die. Similarly, the threshold voltage distribution can be determined internally within the memory die. Optionally, storage elements which become conductive can be locked out, such as by changing a bit line voltage, so they no longer contribute to the characteristic (715). New read reference voltages are determined based on the threshold voltage distribution to reduce errors in future read operations.

Systems and methods for temporarily retiring memory portions

Abstract: Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time.

Systems and methods for averaging error rates in non-volatile devices and storage systems

Abstract: A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

Systems and methods for multiple coding rates in flash devices

Abstract: A system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information arriving from a host for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding rate which is a function of the number of redundancy bytes generated, the encoding including determining an effective error rate, including an anticipated rate of expected reading errors, for the flash memory location; and selecting the encoding rate as a function of the effective error rate such that the number of redundancy bytes is sufficient to overcome the anticipated rate of expected reading errors with a predetermined degree of certainty.