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D. Pala

Bio: D. Pala is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: CPU cache & Cache-only memory architecture. The author has an hindex of 1, co-authored 1 publications receiving 11 citations.

Papers
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Proceedings ArticleDOI
TL;DR: A system-level tool based on CACTI simulator is presented to assist memory system designers to generate high-performance and low-power cache memories comparing performance, energy consumption, and area with traditional SRAM.
Abstract: In the last decade, academies and private companies have actively explored emerging memory technologies STT-MRAM in particular is experiencing a rapid development but it is facing several challenges in terms of performance and reliability Several techniques at cell level have been proposed to mitigate such issues but currently few tools and methodologies exist to support designers in evaluating the impact that specific micro-level design choices can determine on the STT-MRAM macro design In this paper we present a system-level tool based on CACTI simulator to assist memory system designers We use our tool to generate high-performance and low-power cache memories comparing performance, energy consumption, and area with traditional SRAM

12 citations


Cited by
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01 Jan 2012
TL;DR: In this article, two 3D stacking structures built upon bipolar RRAM crossbars are proposed to enable multilayer accesses while avoiding the overwriting induced by the cross-layer disturbance.
Abstract: For its simple structure, high density, and good scalability, the resistive random access memory (RRAM) has emerged as one of the promising candidates for large data storage in computing systems. Moreover, building up RRAM in a 3-D stacking structure further boosts its advantage in array density. Conventionally, multiple bipolar RRAM layers are piled up vertically separated with isolation material to prevent signal interference between the adjacent memory layers. The process of the isolation material increases the fabrication cost and brings in the potential reliability issue. To alleviate the situation, we introduce two novel 3-D stacking structures built upon bipolar RRAM crossbars that eliminate the isolation layers. The bigroup operation scheme dedicated for the proposed designs to enable multilayer accesses while avoiding the overwriting induced by the cross-layer disturbance is also presented. Our simulation results show that the proposed designs can increase the capacity of a memory island to 8K-bits (i.e., eight layers of 32 × 32 crossbar arrays) while maintaining the sense margin in the worst case configuration greater than 20% of the maximal sensing voltage.

22 citations

Proceedings ArticleDOI
05 Jun 2016
TL;DR: A new member of NVSim family is introduced - NVSim-VXs, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption, and strongly supports the fast-growing needs of STt-RAM research on reliability analysis and enhancement.
Abstract: Spin-transfer torque random access memory (STT-RAM) recently received significant attentions for its promising characteristics in cache and memory applications. As an early-stage modeling tool, NVSim has been widely adopted for simulations of emerging nonvolatile memory technologies in computer architecture research, including STT-RAM, ReRAM, PCM, etc. In this work, we introduce a new member of NVSim family -- NVSim-VXs, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption. This enhanced model takes into account the impacts of parametric variabilities of CMOS and MTJ devices and the chip operating temperature. It is also calibrated with Monte-Carlo Simulations based on macro-magnetic and SPICE models, covering five technology nodes between 22nm and 90nm. NVSim-VXs strongly supports the fast-growing needs of STT-RAM research on reliability analysis and enhancement, announcing the next important stage of NVSim development.

17 citations

Journal ArticleDOI
TL;DR: This paper attempts to reduce static power consumption by using non-volatile memory technology-based spin-transfer torque random access memory (STT-RAM) buffers to reduce write variation to almost 0% and improve lifetime by 3.3 and 19.9 times for intra-VNet and inter-V net, respectively.
Abstract: With multiple cores integrated on the same die, communication across cores is managed by on-chip interconnect called network-on-chip (NoC). Power and performance of these interconnect is a significant factor as the communication network consumes a considerable share of the power budget. In particular, the buffers used at every port of the NoC router consume considerable dynamic as well as static power. This paper attempts to reduce static power consumption by using non-volatile memory technology-based spin-transfer torque random access memory (STT-RAM) buffers. STT-RAM technology has the advantage of high density and low leakage but suffers from weaker write endurance. This impacts the lifetime of the router as a whole. The buffers in a router are allocated to virtual networks (VNets) and in-turn to virtual channels (VCs) within each VNet. To reduce uneven writes across the buffers, we propose policies to reduce intra-VNet write variation and inter-VNet write variation. The former performs write variation aware VC allocation in each VNet, and the latter does write variation aware buffer assignments to each VNet. Experimental evaluation on full system simulator shows that proposed policies reduce write variation to almost 0% and improve lifetime by 3.3 and 19.9 times for intra-VNet and inter-VNet, respectively. We also get significant gains in the energy delay product.

4 citations

25 Jan 2018
TL;DR: This work introduces a new member of NVSim family – NVSim-VXs, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption and proposes two possible SHE-RAM designs from the aspects of two different write access operations.
Abstract: DEVELOPING VARIATION AWARE SIMULATION TOOLS, MODELS, AND DESIGNS FOR STT-RAM Enes Eken, PhD University of Pittsburgh, 2017 In recent years, we have been witnessing the rise of spin-transfer torque random access memory (STT-RAM) technology. There are a couple of reasons which explain why STT-RAM has attracted a great deal of attention. Although conventional memory technologies like SRAM, DRAM and Flash memories are commonly used in the modern computer industry, they have major shortcomings, such as high leakage current, high power consumption and volatility. Although these drawbacks could have been overlooked in the past, they have become major concerns. Its characteristics, including low-power consumption, fast read-write access time and non-volatility make STT-RAM a promising candidate to solve the problems of other memory technologies. However, like all other memory technologies, STT-RAM has some problems such as long switching time and large programming energy of Magnetic Tunneling Junction (MTJ) which are waiting to be solved. In order to solve these long switching time and large programming energy problems, Spin-Hall Effect (SHE) assisted STT-RAM structure (SHE-RAM) has been recently invented. In this work, I propose two possible SHE-RAM designs from the aspects of two different write access operations, namely, High Density SHE-RAM and Disturbance Free SHE-RAM, respectively. In addition to the SHE-RAM designs, I will also propose a simulation tool for STT-RAMs. As an early-stage modeling tool, NVSim has been widely adopted for simulations of emerging nonvolatile memory technologies in computer architecture research, including STT-RAM, ReRAM, PCM, etc. I will introduce a new member of NVSim family – NVSim-VXs, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption.

3 citations

Journal ArticleDOI
TL;DR: This work proposes an entire flow for obtaining/calibrating the transistor characteristics from a commercial technology and uses these characteristics within CACTI for the first time, and extends it to support negative capacitance fin field effect transistor (NC-FinFET), an emerging technology depictingnegative capacitance whose current and capacitive characteristics are very different compared to those of the FinFET.
Abstract: Cache memories are an indispensable component of many processor-based systems and contribute significantly to the overall area, power consumption, and delay. This leads to an important role played by modeling tools for estimating the area, power consumption, and access time of cache memories. However, existing modeling tools such as CACTI and its various extensions have been primarily designed using data from various projections. For the first time, we propose an entire flow for obtaining/calibrating the transistor characteristics from a commercial technology and use these characteristics within CACTI. We also improve the modeling approach to make them more fine-grained and follow recent manufacturing trends suitable for FinFET technology. Further, for the first time, we extend CACTI to support negative capacitance fin field effect transistor (NC-FinFET), an emerging technology depicting negative capacitance whose current and capacitive characteristics are very different compared to those of the FinFET. We use the proposed tool (FN-CACTI) to identify NC-FinFET-based caches to be significantly more energy-efficient than corresponding FinFET-based caches. We also study an application of FN-CACTI to determine optimal voltages corresponding to the lowest energy consumption for NC-FinFET and FinFET-based caches of various sizes.

3 citations