D. Pinna

Bio: D. Pinna is an academic researcher from University of Pavia. The author has contributed to research in topics: CMOS & Energy harvesting. The author has an hindex of 5, co-authored 7 publications receiving 80 citations.

Integrated micro-solar cell structures for harvesting supplied microsystems in 0.35-µm CMOS technology

Abstract: In this paper we present a solar harvester test chip, realized to characterize several integrated solar cell structures, gathering the information required to design a complete power management system for handling the harvested energy. In particular, we realized photodiodes with three different geometries of the p-diffusion, and three different dimensions of the n-well. The chip is realized in a 0.35-µm CMOS technology, and the diodes feature different active area density, depending on the geometry of the p-diffusions. In order to evaluate the harvesting performance of the solar cells in real applications, we developed an equivalent circuit of the devices, based on the experimental data and we used it to design a power management system specific for discrete-time applications. The power management system is being integrated on the same chip of the micro solar cells, in a 0.35-µm CMOS technology.

A 0.35μm CMOS Solar energy scavenger with power storage management system

Abstract: In this paper we present an integrated solar energy scavenger realized in a 0.35 μm CMOS technology. The proposed system collects solar energy from the environment through integrated diodes, accumulates it and, delivers it to the load when it is enough to allow proper operation of the CMOS circuitry. The proposed system is suitable for discrete-time regime applications, such as sensor network nodes or, generally, systems that require power supply periodically for short time slots. In order to properly design the system, we developed a model of the integrated solar cell on the basis of measurement data extracted from a test chip. The power management circuit, including a charge pump a comparator and a linear voltage regulator, has been extensively simulated.

Integrated stabilized photovoltaic energy harvester

Abstract: In this paper a photovoltaic power generator is presented. The energy harvesting device exploits the power generated by several on-chip micro-photovoltaic cells, connected in series, to provide the supply voltage and the reference voltages for an integrated voltage regulator. The regulator operates also with low illumination levels or large load currents, and tolerates a wide variation of the voltage produced by the micro-photovoltaic cell chain. In order to allow the series connection of several photovoltaic cells, we used an SOI technology, where parasitic p-n junctions to the substrate are not present.

Model of integrated micro photovoltaic cell structures for harvesting supplied microsystems in 0.35-µm CMOS technology

Abstract: In this paper we present a micro photovoltaic cell model, validated by the experimental results obtained from a test chip realized in 035-µm CMOS technology In particular, we analyzed and modeled the behavior of an integrated p-n junction when irradiated with incident light with solar spectrum, considering the parameters of a conventional 035-µm CMOS technology We considered the effect of irradiation on the basic diode equation, which allows the estimation of the carrier photo-generation as a function of the geometrical parameters of the micro photovoltaic cell This model is particularly useful to predict the available harvested power that can be delivered to an on-chip integrated microsystem Based on the proposed model, we also developed an equivalent circuit of the micro photovoltaic cells, that can be used with circuit simulators to evaluate the performance of complete microsystems The test chip realized to validate the model consists of a set of different integrated micro photovoltaic cells

Integrated self-supplied system for environmental temperature sensing

Abstract: In this paper we present a 4-mm2 battery-less temperature sensor, designed to collect and periodically transmit information to an ambient monitoring system. It consists of a 0.35-µm BCD SOI technology based chip including an ultra-low power integrated circuit and an energy harvesting supply unit made by 34 series-parallel connected photovoltaic cells. Each cell consists of a trench insulated p-n junction. Series connections among cells are possible because of the lack, guaranteed by the SOI insulation, of the substrate parasitic diode, typical in standard CMOS technology. The system is fully compliant with real-time applications and can work in low illumination conditions and with large variations of the photovoltaic voltage.

An Inductorless DC–DC Converter for Energy Harvesting With a 1.2- $ \mu\hbox{W}$ Bandgap-Referenced Output Controller

Abstract: We present a fully integrated dc-dc converter for micropower energy harvesting. A 1.2- μW bandgap-referenced output controller provides output regulation at 1.4 V, achieving quiescent power of 3 μW and a maximum overall efficiency of 58% at 11 μW output power. A modified four-phase charge pump provides a 3× voltage boost and a minimum input voltage of 270 mV in free-running mode. Using dual switches driven from both the converter input and output, the chip achieves boost without external excitation or external components.

A Nanocurrent Power Management IC for Multiple Heterogeneous Energy Harvesting Sources

Abstract: This paper presents a fully autonomous power converter IC for energy harvesting from multiple and multitype sources, such as piezoelectric, photovoltaic, thermoelectric, and RF transducers. The converter performs an independent self-adapting input power tracking process for each source. The peak power conversion efficiency measured during single-source operation is 89.6%. With all sources enabled, the intrinsic current consumption is as low as 47.9 nA/source. A self-starting battery-less architecture has been implemented in a 0.32-μm STMicroelectronics BCD technology with a 2142 μm × 2142 μm die area. The IC only requires a single-shared inductor and an external storage capacitor for the basic working configuration. With respect to other multisource energy harvesters, this design specifically introduces a series of nanopower design techniques for extreme minimization of the intrinsic consumption during operation. The small chip size combined with the limited number of required external component, the high conversion efficiency, and the state-of-the-art intrinsic nanocurrent consumption make the IC suitable for many critical applications with very limited available power, such as wearable devices or unobtrusive wireless sensor networks.

A Sub- ${\boldsymbol kT}/\boldsymbol q$ Voltage Reference Operating at 150 mV

Abstract: We propose a subthreshold CMOS voltage reference operating with a minimum supply voltage of only 150 mV, which is three times lower than the minimum value presently reported in the literature. The generated reference voltage is only 17.69 mV. This result has been achieved by introducing a temperature compensation technique that does not require the drain–source voltage of each MOSFET to be larger than $4 kT/q$ . The implemented solution consists in two transistors voltage reference with two MOSFETs of the same threshold-type and exploits the dependence of the threshold voltage on transistor size. Measurements performed over a large sample population of 60 chips from two separate batches show a standard deviation of only 0.29 mV. The mean variation of the reference voltage for $V_{\rm DD}$ ranging from 0.15 to 1.8 V is 359.5 $\mu $ V/V, whereas the mean variation of V $_{\rm {REF}}$ in the temperature range from 0 °C to 120 °C is 26.74 $\mu $ V/°C. The mean power consumption at 25 °C for $V_{\rm DD}= 0.15$ V is 26.1 pW. The occupied area is $1200~\mu $ m $^{2}$ .

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

Abstract: An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

Transactions Briefs A Sub-kT/q Voltage Reference Operating at 150 mV

Abstract: We propose a subthreshold CMOS voltage reference oper- ating with a minimum supply voltage of only 150 mV, which is three times lower than the minimum value presently reported in the literature. The generated reference voltage is only 17.69 mV. This result has been achieved by introducing a temperature compensation technique that does not require the drain-source voltage of each MOSFET to be larger than 4kT/q. The implemented solution consists in two transistors voltage reference with two MOSFETs of the same threshold-type and exploits the dependence of the threshold voltage on transistor size. Measurements performed over al arge sample population of 60 chips from two separate batches show a standard deviation of only 0.29 mV. The mean variation of the reference voltage for VDD ranging from 0.15 to 1.8 V is 359.5 µV/V, whereas the mean variation of VREF in the temperature range from 0 °C to 120 °C is 26.74 µV/°C. The mean power consumption at 25 °C for VDD = 0.15 V is 26.1 pW. The occupied area is 1200 µm 2 .