D. Rechem

Bio: D. Rechem is an academic researcher. The author has contributed to research in topics: Threshold voltage & Subthreshold slope. The author has an hindex of 2, co-authored 2 publications receiving 26 citations.

Channel length scaling and the impact of metal gate work function on the performance of double gate-metal oxide semiconductor field-effect transistors

Abstract: In this paper, we study the effects of short channel on double gate MOSFETs. We evaluate the variation of the threshold voltage, the subthreshold slope, the leakage current and the drain-induced barrier lowering when channel length LCH decreases. Furthermore, quantum effects on the performance of DG-MOSFETs are addressed and discussed. We also study the influence of metal gate work function on the performance of nanoscale MOSFETs. We use a self-consistent Poisson-Schrodinger solver in two dimensions over the entire device. A good agreement with numerical simulation results is obtained.

THE EFFECT OF SHORT CHANNEL ON NANOSCALE SOI MOSFETs

Abstract: Double gate silicon-on-insulator (DG SOI) devices have recently been of great interest, particularly for the investigation of sub-10nm field-effect transistor [1]-[3]. As the channel length is reduced from one transistor generation to the next, the susceptibility of the transistor to short-channel effects (SCE) is monitored in several ways such as threshold voltage (VTH) roll-off, sub-threshold voltage swing, and the drain induced barrier low, the channel length decreases and becomes crucial in deep-submicrometer technologies. As an indicator of these short channel effects, the threshold voltage and sub-threshold voltage swing has been extensively investigated [4]-[7]. In order to maintain a tolerable degree of short channel effect [8], it becomes necessary to reduce the SOI film thickness. Reducing the SOI film thickness causes a high electric field in the perpendicular direction to the Si/SiO2 interface, strongly confining charge carriers in the channel. Several interesting models have been proposed for the classical (i.e., without quantum effects) drain current [9]-[11]. Carrier quantization effects have been considered for the first time in [12]. Therefore, classical models that disregard these effects are no longer suitable for describing sub 10nm MOSFETs. Therefore, we use quantum mechanical transport models for n-channel MOSFETs based on the self-consistent Schrodinger and Poisson equations for the simulation of short channel effects on the performance of DGMOSFET. In addition to it, the model is continuous over all gate and drain bias ranges, which makes it very suitable to simulate novel silicon transistor structures. 2. Results

3-D Analytical Modeling of Dual-Material Triple-Gate Silicon-on-Nothing MOSFET

Abstract: A 3-D analytical model of a new structure, namely, dual-material triple-gate silicon-on-nothing MOSFET is proposed in this paper. 3-D Poisson’s equation with proper boundary conditions was solved to obtain the surface potential variation of the structure considering the popular parabolic potential approximation, and the threshold voltage and electric field were calculated for the model. The proposed model’s immunity to the various short-channel effects, such as threshold voltage roll-off, Drain-Induced Barrier Lowering (DIBL), and subthreshold swing, are also examined, and the impact of the various device parameters on the performance of the device is studied. The 3-D simulated results obtained using ATLAS, a device simulator from Silvaco, validate the analytical results obtained for this structure.

Analytical modeling of trilayer graphene nanoribbon Schottky-barrier FET for high-speed switching applications

Abstract: Recent development of trilayer graphene nanoribbon Schottky-barrier field-effect transistors (FETs) will be governed by transistor electrostatics and quantum effects that impose scaling limits like those of Si metal-oxide-semiconductor field-effect transistors. The current–voltage characteristic of a Schottky-barrier FET has been studied as a function of physical parameters such as effective mass, graphene nanoribbon length, gate insulator thickness, and electrical parameters such as Schottky barrier height and applied bias voltage. In this paper, the scaling behaviors of a Schottky-barrier FET using trilayer graphene nanoribbon are studied and analytically modeled. A novel analytical method is also presented for describing a switch in a Schottky-contact double-gate trilayer graphene nanoribbon FET. In the proposed model, different stacking arrangements of trilayer graphene nanoribbon are assumed as metal and semiconductor contacts to form a Schottky transistor. Based on this assumption, an analytical model and numerical solution of the junction current–voltage are presented in which the applied bias voltage and channel length dependence characteristics are highlighted. The model is then compared with other types of transistors. The developed model can assist in comprehending experiments involving graphene nanoribbon Schottky-barrier FETs. It is demonstrated that the proposed structure exhibits negligible short-channel effects, an improved on-current, realistic threshold voltage, and opposite subthreshold slope and meets the International Technology Roadmap for Semiconductors near-term guidelines. Finally, the results showed that there is a fast transient between on-off states. In other words, the suggested model can be used as a high-speed switch where the value of subthreshold slope is small and thus leads to less power consumption.