D
D. Towner
Researcher at Intel
Publications - 4
Citations - 1024
D. Towner is an academic researcher from Intel. The author has contributed to research in topics: Logic gate & CMOS. The author has an hindex of 3, co-authored 4 publications receiving 941 citations.
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Proceedings ArticleDOI
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
C. Auth,C. Allen,A. Blattner,Daniel B. Bergstrom,Mark R. Brazier,M. Bost,M. Buehler,V. Chikarmane,Tahir Ghani,Timothy E. Glassman,R. Grover,W. Han,D. Hanken,Michael L. Hattendorf,P. Hentges,R. Heussner,J. Hicks,D. Ingerly,Pulkit Jain,S. Jaloviar,Robert James,David Jones,J. Jopling,Subhash M. Joshi,C. Kenyon,Huichu Liu,R. McFadden,B. McIntyre,J. Neirynck,C. Parker,L. Pipes,Ian R. Post,S. Pradhan,M. Prince,S. Ramey,T. Reynolds,J. Roesler,J. Sandford,J. Seiple,Pete Smith,Christopher D. Thomas,D. Towner,T. Troeger,Cory E. Weber,P. Yashar,K. Zawadzki,Kaizad Mistry +46 more
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Proceedings ArticleDOI
45nm High-k + metal gate strain-enhanced transistors
C. Auth,Annalisa Cappellani,J.-S. Chun,A. Dalis,Alison Davis,Tahir Ghani,G. Glass,Timothy E. Glassman,Michael K. Harper,Michael L. Hattendorf,P. Hentges,S. Jaloviar,Subhash M. Joshi,Jason Klaus,K. Kuhn,D. Lavric,M. Lu,H. Mariappan,Kaizad Mistry,B. Norris,Nadia M. Rahhal-Orabi,Pushkar Ranade,J. Sandford,Lucian Shifren,V. Souw,K. Tone,F. Tambwe,A. Thompson,D. Towner,T. Troeger,P. Vandervoorn,Charles H. Wallace,J. Wiedemer,Christopher J. Wiegand +33 more
TL;DR: In this article, two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper.
Proceedings ArticleDOI
A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors
C.-H. Jan,P. Bai,S. Biswas,M. Buehler,Zhanping Chen,G. Curello,S. Gannavaram,Hafez Walid M,Jun He,J. Hicks,U. Jalan,N. Lazo,J. Lin,Nick Lindert,C. Litteken,M. Jones,M. Kang,K. Komeyli,A. Mezhiba,S. Naskar,S. Olson,Joodong Park,Rachael J. Parker,L. Pei,Ian R. Post,N. Pradhan,Chetan Prasad,M. Prince,J. Rizk,G. Sacks,H. Tashiro,D. Towner,C. Tsai,Yih Wang,L. Yang,J.-Y. Yeh,J. Yip,Kaizad Mistry +37 more
TL;DR: A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products.
Proceedings ArticleDOI
Reliability Characteristics of a High Density Metal- Insulator-Metal Capacitor on Intel’s 10+ Process
Che-Yun Lin,U. E. Avci,M. A. Blount,R. Grover,J. Hicks,Rahim Kasim,A. Kundu,C. M. Pelto,C. Ryder,A. Schmitz,K. Sethi,D. Seghete,D. Towner,A. J. Welsh,J. R. Weber,C. Auth +15 more
TL;DR: This high density MIM decoupling capacitor improves the on-chip power delivery network, leading to an increase in maximum frequency of microprocessors and is now shipping in volume.