Dan Kinzer

Bio: Dan Kinzer is an academic researcher from Fairchild Semiconductor International, Inc.. The author has contributed to research in topics: Die (integrated circuit) & Integrated circuit packaging. The author has an hindex of 5, co-authored 8 publications receiving 68 citations.

Challenges of power electronic packaging and modeling

Abstract: Power electronic packaging is one of the fastest changing areas of technology in the power electronic industry due to the rapid advances in power integrated circuit (IC) fabrication and the demands of a growing market in almost all areas of power electronic application such as portable electronics, consumer electronics, home electronics, computing electronics, automotive, railway and high/strong power industry. However, due to the intrinsic high power dissipation, the performance requirement for power products are extremely high, especially in handling harsh thermal and electrical environments. The design rules and material and structure layout of power packaging are quite different from regular IC packaging. This talk will present a state-of-art and in-depth overview of recent advances, challenges and opportunities in power electronic packaging design and modeling. A review of recent advances in power electronic packaging is presented based on the development of power device integration. The talk will cover in more detail how challenges in both semiconductor content and advanced power package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.

Wafer level stack die package

Abstract: This document discusses, among other things, an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.

Modeling for critical design and performance of wafer level chip scale package

Abstract: Comprehensive finite element analysis (FEA) modeling is carried out to improve the performance of critical designs of wafer level chip scale package (WLCSP). First, a design with one layer redistribution layout (RDL) copper with etched pocket in the non-covered UBM area and one layer polyimide structure (1Cu1Pi design) is investigated. Different polyimide layouts, copper thicknesses, pocket parameters and non-covered UBM diameters are studied through finite element modeling. Then, a stacked metal design with the sputtered copper UBM stacked on the RDL copper layer, with one polyimide layer between them (2Cu1Pi) for the WLCSP is examined. Parameter study of different UBM diameters with the same solder volume and different UBM diameters with the same solder joint height is conducted by the simulation. Finally the correlation and comparison of the failure mechanism between the modeling and the test are presented and discussed.

SiC BJT minimizes losses in alternative energy applications

Abstract: Technologies such as Plug-in Hybrid Electric Vehicles (PHEV), Photovoltaics (PV), high efficiency electric motor drives, etc. will reduce energy related emissions and US dependency on fossil fuels and foreign oil. However commercial adoption of these technologies is slow to start due to high price and long financial payback. Silicon (Si) based power electronic systems in the above mentioned technologies form a significant part of the high price. New wide band gap devices such as Silicon Carbide (SiC) transistors are being considered (needed) as an alternative to Si transistors to improve energy efficiency, reduce passive component and thermal management size and cost, and thus reduce the overall cost of ownership to the end consumer. This paper will discuss the Bipolar Junction Transistor (BJT) as a suitable device type that is ideally suited for the widespread adoption of SiC transistors.

Modeling for defects impact on electrical performance of power packages

Abstract: The electrical performance (such as electrical resistance, inductance and fusing current capability) is a key factor for a power electronic product. Studying the impact of the defect on package electrical performance, especially for the parasitic effect is very important. It can help to understand the potential root causes and failure mechanisms, as well as to ensure the electrical performance meets the product requirements by optimizing the package design and assembly process. The objective of this paper is to study the impact of wire bonding-related defects and the die attach solder voids for the electrical resistance, inductance and fusing current capability of the power packages. The major work in this paper consists of two parts. One is the impact of wire bonding-related defects on the electrical performance of the power package. The other is the impact of die attach (DA) solder void. Both electrical and coupled thermal electrical simulations are conducted to study the wire bonding-related defects and DA solder voids of different levels. Simulation results show that the resistance and inductance of the package are not sensitive to the wire bond defects. However, the wire bond defects may induce significant impact on the fusing current capability of the package. For die attach voids, the inductance of the package seems not sensitive to the die attach voids while the electrical resistance has been affected significantly.

POP Structures and Methods of Forming the Same

Abstract: A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.

Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs

Abstract: The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate. At low voltages (below 100 V), the silicon (Si) MOSFET reigns supreme and at the higher end of the automotive medium-voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the Si insulated-gate bipolar transistor (IGBT). At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs, and enhancement mode GaN high electron mobility transistors (HEMTs). Each technology comes with its unique selling point with gallium nitride (GaN) being well known for ultrahigh speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness, and fast switching while silicon remains clearly dominant in cost and proven reliability. This article comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability, and avalanche ruggedness.

Gate and Base Drivers for Silicon Carbide Power Transistors: An Overview

Abstract: Silicon carbide (SiC) power transistors have started gaining significant importance in various application areas of power electronics. During the last decade, SiC power transistors were counted not only as a potential, but also more importantly as an alternative to silicon counterparts in applications where high efficiency, high switching frequencies, and operation at elevated temperatures are targeted. Various SiC device designs have been proposed and excessive investigations in terms of simulation and experimental studies have shown their advantageous performance compared to silicon technology. On a system-level, however, the design of gate and base drivers for SiC power transistors is very challenging. In particular, a sophisticated driver design is not only associated with properly switching the transistor and decreasing the switching power losses, but also it must incorporate protection features, as well as comply with the electromagnetic compatibility. This paper shows an overview of the gate and base drivers for SiC power transistors which have been proposed by several highly qualified scientists. In particular, the basic operating principle of each driver along with their applicability and drawbacks are presented. For this overview, the three most successful SiC power transistors are considered: junction-field-effect transistors, bipolar-junction transistors, and metal-oxide-semiconductor field-effect transistors. Last but not least, future challenges on gate and base drivers design are also presented.

High Performance Silicon Carbide Power Packaging—Past Trends, Present Practices, and Future Directions

Abstract: This paper presents a vision for the future of 3D packaging and integration of silicon carbide (SiC) power modules. Several major achievements and novel architectures in SiC modules from the past and present have been highlighted. Having considered these advancements, the major technology barriers preventing SiC power devices from performing to their fullest ability were identified. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were described, and the concept for a novel SiC power module was discussed.

Fan-out wafer level package structure

Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.