Dan Ozawa

Bio: Dan Ozawa is an academic researcher from Yokohama National University. The author has contributed to research in topics: Adiabatic process & Dissipation. The author has an hindex of 1, co-authored 1 publications receiving 209 citations.

An adiabatic quantum flux parametron as an ultra-low-power logic device

Abstract: Ultra-low-power adiabatic quantum flux parametron (QFP) logic is investigated since it has the potential to reduce the bit energy per operation to the order of the thermal energy. In this approach, nonhysteretic QFPs are operated slowly to prevent nonadiabatic energy dissipation occurring during switching events. The designed adiabatic QFP gate is estimated to have a dynamic energy dissipation of 12% of IcΦ0 for a rise/fall time of 1000 ps. It can be further reduced by reducing circuit inductances. Three stages of adiabatic QFP NOT gates were fabricated using a Nb Josephson integrated circuit process and their correct operation was confirmed.

Superconductor digital electronics: Scalability and energy efficiency issues (Review Article)

Abstract: Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin s...

Beyond Moore's technologies: operation principles of a superconductor alternative.

Abstract: The predictions of Moore's law are considered by experts to be valid until 2020 giving rise to "post-Moore's" technologies afterwards. Energy efficiency is one of the major challenges in high-performance computing that should be answered. Superconductor digital technology is a promising post-Moore's alternative for the development of supercomputers. In this paper, we consider operation principles of an energy-efficient superconductor logic and memory circuits with a short retrospective review of their evolution. We analyze their shortcomings in respect to computer circuits design. Possible ways of further research are outlined.

Superconductor Digital Electronics: Scalability and Energy Efficiency Issues

Abstract: Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin superconducting layer for making compact high-kinetic-inductance bias inductors. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The physical limitations imposed on the circuit density by Josephson junctions, circuit inductors, shunt and bias resistors, etc., are discussed. Energy dissipation in superconducting circuits is also reviewed in order to estimate whether this technology, which requires cryogenic refrigeration, can be energy efficient. Fabrication process development required for increasing the density of superconductor digital circuits by a factor of ten and achieving densities above 10^7 Josephson junctions per cm^2 is described.

Adiabatic quantum-flux-parametron cell library designed using a 10 kA cm−2 niobium fabrication process

Abstract: Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power consumption and very small switching energy. In this paper, we report a new AQFP cell library designed using the AIST 10 kA cm−2 Nb high-speed standard process (HSTP), which is a high-critical-current–density version of the AIST 2.5 kA cm−2 Nb standard process (STP2). Since the intrinsic damping of the Josephson junction (JJ) of HSTP is relatively strong, shunt resistors for JJs were removed and the energy efficiency improved significantly. Also, excitation transformers in the new cells were redesigned so that the cells can operate in a four-phase excitation mode. We described the detail of HSTP and the AQFP cell library designed using HSTP, and showed experimental results of cell test circuits.

Quantum-classical interface based on single flux quantum digital logic

Abstract: We describe an approach to the integrated control and measurement of a large-scale superconducting multiqubit circuit using a proximal coprocessor based on the Single Flux Quantum (SFQ) digital logic family. Coherent control is realized by irradiating the qubits directly with classical bitstreams derived from optimal control theory. Qubit measurement is performed by a Josephson photon counter, which provides access to the classical result of projective quantum measurement at the millikelvin stage. We analyze the power budget and physical footprint of the SFQ coprocessor and discuss challenges and opportunities associated with this approach.