Daniel Llamocca Obregon

Bio: Daniel Llamocca Obregon is an academic researcher. The author has contributed to research in topics: Block (data storage) & Adder. The author has an hindex of 2, co-authored 3 publications receiving 13 citations.

System and methods for dynamic management of hardware resources

Abstract: A dynamically reconfigurable framework manages processing applications in order to meet time-varying constraints to select an optimal hardware architecture. The optimal architecture satisfies time-varying constraints including for example, supplied power, required performance, accuracy levels, available bandwidth, and quality of output such as image reconstruction. The process of determining an optimal solution is defined in terms of multi-objective optimization using Pareto-optimal realizations.

System and methods for computing forward and inverse discrete periodic radon transform

Abstract: A fast and a scalable approach for computing the forward and inverse DPRT that uses: (i) a parallel array of fixed-point adder trees to compute the additions, (ii) circular shift registers to remove the need for accessing external memory components, (iii) an image block-based approach to DPRT computation that can fit the proposed architecture to available resources, and (iv) fast transpositions that are computed in one or a few clock cycles that do not depend on the size of the input image.

System and methods for computing 2-d convolutions and cross-correlations

Abstract: Fast and scalable architectures and methods adaptable to available resources, that (1) compute 2-D convolutions using 1-D convolutions, (2) provide fast transposition and accumulation of results for computing fast cross-correlations or 2-D convolutions, and (3) provide parallel computations using pipelined 1-D convolvers. Additionally, fast and scalable architectures and methods that compute 2-D linear convolutions using Discrete Periodic Radon Transforms (DPRTs) including the use of scalable DPRT, Fast DPRT, and fast 1-D convolutions.

Embedded systems of internet-of-things incorporating a cloud computing service of FPGA reconfiguration

Abstract: IoT embedded systems as well as cloud computing infrastructure may merge processor soft cores with programmable logic (FPGAs) to yield a heterogeneous hardware-software processing ecosystem through which the embedded systems and infrastructure customize and adapt their computational power to the specific application in use. The embedded systems and cloud computing infrastructure with dynamic reconfiguration will bring neuroplasticity to the interconnected space of IoT embedded systems, enabling high-performance, customized, secure-by-design cloud computing services. A cloud server of IaaS is employed to evaluate the performances and efficiencies of embedded systems according to its hardware architectures, so that the computing service allow one reconfigurable system download its hardware architecture file or bitstream into other embedded systems via the cloud server.

Dynamically reconfigurable logic circuits using native field-programmable gate array primitives

Abstract: A method for dynamically reconfiguring logic circuits on an FPGA includes the steps of: classifying a general function into sets of static functions and modal functions to be implemented on the FPGA; for each of the modal functions, generating a list of one-active actions; devising a circuit topology including at least a subset of look-up tables (LUTs) such that any one of the modal functions can be implemented at a time on the devised circuit topology; for each modal function, associating the devised circuit topology with a controller adapted to load a LUT configuration corresponding to a prescribed one of the one-active actions; implementing a single fixed circuit on the FPGA including devised circuit topologies for each of the modal functions; and updating contents of LUTs corresponding to the LUT configuration in the devised circuit topology when a change in modal function to be implemented on the FPGA is required.

Offloading projection of fixed and variable length database columns

Abstract: In an exemplary embodiment of this disclosure, a computer-implemented method includes determining that a database query warrants a first projection operation to project a plurality of input rows to a plurality of projected rows, where each of the plurality of input rows has one or more variable-length columns. A first projection control block is constructed, by a computer processor, to describe the first projection operation. The first projection operation is offloaded to a hardware accelerator. The first projection control block is provided to the hardware accelerator, and the first projection control block enables the hardware accelerator to perform the first projection operation at streaming rate.

Hardware projection of fixed and variable length columns of database tables

Abstract: In an exemplary embodiment of this disclosure, a computer-implemented method includes receiving, at a hardware accelerator, a first instruction to project a first plurality of database rows, where each of the first plurality of database rows has one or more variable-length columns The first plurality of database rows are projected, by a computer processor, to produce a first plurality of projected rows This projection is performed at streaming rate

Dynamic-data general framework facing embedded system development

Abstract: The invention discloses a dynamic-data general framework facing embedded system development. The dynamic-data general framework comprises a resource manager for being responsible for providing data in the global range, a virtual loader for dynamically loading classes in a dex file or classes in an external file and obtaining required sources through the resource manager and a view binder for binding different-type data provided by the virtual loader to corresponding controls. By means of the dynamic-data general framework facing embedded system development, the code quantity can be reduced, and the code reliability is improved; the logical structure can be clear, a data business process and other logic (view logic and the like) are separated, and the testability of codes is improved.