David D. Ling

Bio: David D. Ling is an academic researcher from IBM. The author has contributed to research in topics: Waveform & Model order reduction. The author has an hindex of 8, co-authored 11 publications receiving 641 citations. Previous affiliations of David D. Ling include University of Chicago.

Power supply noise analysis methodology for deep-submicron VLSI chip design

Abstract: This paper describes a new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors.Based on an integrated package-level andchip-level power bus model, and a simulated switching circuitmodel for each functional block, this methodology offersthe most complete and accurate analysis of Vdd distributionfor the entire chip. The analysis results not only providedesigners with the inductive ΔI noise and the resistive IRdrop data at the same time, but also allow designers to easilyidentify the hot spots on the chip and ΔV across the chip.Global and local optimization such as buffer sizing, powerbus sizing, and on-chip decoupling capacitor placement canthen be conducted to maximize the circuit performance andminimize the noise.

A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks

Abstract: Recent work in the area of model-order reduction for RLC interconnect networks has been focused on building reduced-order models that preserve the circuit-theoretic properties of the network, such as stability, passivity, and synthesizability. Passivity is the one circuit-theoretic property that is vital for the successful simulation of a large circuit netlist containing reduced-order models of its interconnect networks. Non-passive reduced-order models may lead to instabilities even if they are themselves stable. In this paper, we address the problem of guaranteeing the accuracy and passivity of reduced-order models of multiport RLC networks at any finite number of expansion points. The novel passivity-preserving model-order reduction scheme is a block version of the rational Arnoldi algorithm. The scheme reduces to that of the PRIMA algorithm when applied to a single expansion point at zero frequency. Although the treatment of this paper is restricted to expansion points that are on the negative real axis, it is shown that the resulting passive reduced-order model is superior in accuracy to the one that would result from expanding the original model around a single point. Nyquist plots are used to illustrate both the passivity and the accuracy of the reduced-order models.

Efficient full-wave electromagnetic analysis via model-order reduction of fast integral transforms

Abstract: An efficient full-wave electromagnetic analysis tool would be useful in many aspects of engineering design. Development of integral-equation based tools has been hampered by the high computational complexity of dense matrix representations and difficulty in obtaining and utilizing the frequency-domain response. In this paper we demonstrate that an algorithm based on application of a novel model-order reduction scheme directly to the sparse model generated by a fast integral transform has significant advantages for frequency- and time-domain simulation.

Zeros and passivity of Arnoldi-reduced-order models for interconnect networks

Abstract: CAD tools and research in the area of reduced-ordermodeling of large linear interconnect networks have evolvedfrom merely finding a Pad' e approximation for the givennetwork transfer function to finding an approximate transferfunction that preserves such circuit-theoretic propertiesof the network as stability, passivity, and RLC synthesizability.In particular, preserving passivity guarantees thatthe reduced-order models will be well-behaved when embeddedback in the circuit where the interconnect networkoriginated. While stability can be ascertained by studyingthe poles of the reduced-order transfer function, passivitydepends on both the poles and zeros of the networkdriving-point impedance. In this paper, we present a novelmethod for studying the zeros of reduced-order transferfunctions and show how it yields conclusions about passivityand synthesizability. Moreover, in order to obtain aguaranteed-passive reduced-order model for multiport RCnetworks, a new algorithm based on the Arnoldi iteration ispresented. This algorithm is as computationallyefficient asthe one used to generate guaranteed-stable reduced-ordermodels [Coordinate-transformed Arnoldi for generating guranteed stable reduced-order models for RLC circuits].

C3DSTAR: a 3D wiring capacitance calculator

Abstract: A description is given of C3DSTAR, a capacitance program for three-dimensional configurations of conductors and dielectrics, that incorporates a hybrid integral-equation solution of the capacitance problem. The hybrid method combines the use of multilayer Green's function treatment of the infinite planar dielectric interfaces with an explicit treatment of the bound charge at finite and/or irregular dielectric interfaces. The approach described differs from previous hybrid integral equation methods in that the free charge density is the primary unknown, rather than the total charge density. This allows early elimination of numerically induced asymmetry in the capacitance matrix and results in more accurate capacitive values. >

PRIMA: passive reduced-order interconnect macromodeling algorithm

Abstract: This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. The approach proposed here, PRIMA, is a general method for obtaining passive reduced-order macromodels for linear RLC systems. In this paper, PRIMA is demonstrated in terms of a simple implementation which extends the block Arnoldi technique to include guaranteed passivity while providing superior accuracy. While the same passivity extension is not possible for MPVL, comparable accuracy in the frequency domain for all examples is observed.

Simulation of high-speed interconnects

Abstract: With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail.

High-performance CMOS variability in the 65-nm regime and beyond

Abstract: Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed. Process-, device-, and circuit-level responses to systematic and random components of tolerance are considered. Exploratory, novel structures emerging as evolutionary CMOS replacements are likely to change the nature of variability in the coming generations.