Internet of Things (IoT), also referred to as the Internet of Objects, is envisioned as a transformative approach for providing numerous services. Compact smart devices constitute an essential part of IoT. They range widely in use, size, energy capacity, and computation power. However, the integration of these smart things into the standard Internet introduces several security challenges because the majority of Internet technologies and communication protocols were not designed to support IoT. Moreover, commercialization of IoT has led to public security concerns, including personal privacy issues, threat of cyber attacks, and organized crime. In order to provide a guideline for those who want to investigate IoT security and contribute to its improvement, this survey attempts to provide a comprehensive list of vulnerabilities and countermeasures against them on the edge-side layer of IoT, which consists of three levels: (i) edge nodes, (ii) communication, and (iii) edge computing. To achieve this goal, we first briefly describe three widely-known IoT reference models and define security in the context of IoT. Second, we discuss the possible applications of IoT and potential motivations of the attackers who target this new paradigm. Third, we discuss different attacks and threats. Fourth, we describe possible countermeasures against these attacks. Finally, we introduce two emerging security challenges not yet explained in detail in previous literature.

A Comprehensive Study of Security of Internet-of-Things

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. 

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. 

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.




* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

Three-Dimensional Integrated Circuit Design

A 60-GHz wideband circularly polarized (CP) helical antenna array of 4 × 4 elements is designed and fabricated using low temperature cofired ceramic (LTCC) technology. The flexible via hole distribution is fully utilized to achieve a helical antenna array to obtain good circular polarization performance. Meanwhile, grounded coplanar waveguide (GCPW) to stripline is utilized for probe station measurement. Unlike traditional helical antennas, the proposed helical antenna array is convenient for integrated applications. The fabricated antenna array has dimension of 12 × 10 × 2 mm3. The simulated and measured impedance, axial ratio (AR) and radiation pattern are studied and compared. The proposed antenna array shows a wide measured impedance bandwidth from 52.5 to 65.5 GHz for | S11| <; -10dB, wideband measured AR bandwidth from 54 to 66 GHz for AR <;3 dB, respectively.

60-GHz LTCC Integrated Circularly Polarized Helical Antenna Array

A 4 $\,\times\,$ 4 L-probe patch antenna array using multilayer low temperature co-fired ceramic (LTCC) technology is presented for 60-GHz band applications. The proposed antenna array is designed with a high gain in the impedance bandwidth by introducing a novel soft-surface structure. The soft-surface structure comprised of metal strips and via fences reduces the losses caused by severe surface waves and mutual coupling between adjacent elements to improve the radiation performance. The proposed antenna array is convenient for integrated applications. The fabricated antenna array excluding the measurement transition has dimension of 14.4 $\,\times\,$ 14.4 $\,\times\,$ 1 mm $^{3}$ . The simulated and measured impedance and radiation performance are studied and compared. Good agreement is achieved between simulation and measurement. The proposed antenna array shows a wide simulated impedance of 29% from 53 GHz to 71 GHz for $\vert {S}_{11}\vert dB, measured broadband 3-dB gain bandwidth of 18.3% from 54.5 GHz to 65.5 GHz and the gain up to 17.5 dBi at 60 GHz, respectively.

Wideband High-Gain 60-GHz LTCC L-Probe Patch Antenna Array With a Soft Surface

Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems being designed with battery considerations in mind, minimizing the energy consumed in on-chip interconnects becomes crucial. Further, the use of nanometer technologies is making it increasingly important to consider reliability issues during the design of SoC communication architectures. Continued supply voltage scaling has led to decreased noise margins, making interconnects more susceptible to noise sources such as crosstalk, power supply noise, radiation induced defects, etc. The resulting transient faults cause the interconnect to behave as an unreliable transport medium for data signals. Therefore, fault tolerant communication mechanism, such as Automatic Repeat Request (ARQ), Forward Error Correction (FEC), etc., which have been widely used in the networking community, are likely to percolate to the SoC domain. This paper presents a survey of techniques for energy efficient on-chip communication. Techniques operating at different levels of the communication design hierarchy are described, including circuit-level techniques, such as low voltage signaling, architecture-level techniques, such as communication architecture selection and bus isolation, system-level techniques, such as communication based power management and dynamic voltage scaling for interconnects, and network-level techniques, such as error resilient encoding for packetized on-chip communication. Emerging technologies, such as Code Division Multiple Access (CDMA) based buses, and wireless interconnects are also surveyed.

A survey of techniques for energy efficient on-chip communication

From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

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The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

The performance of a system depends heavily on the communication speed between integrated circuits. One of the most important bottlenecks that limit the communication speed is simultaneous switching noise (SSN). A major contribution to SSN is return path discontinuities, which are caused by the change or disruption in return currents due to via transitions, aperture effects, etc. In this paper, a new concept based on power transmission line (PTL) is proposed to supply power, improve signal and power integrity, and enhance chip-to-chip communication speed. The first demonstration of constant current PTL (CCPTL)-based single-ended signaling scheme is implemented and measured. The results show that the CCPTL scheme improves the quality of the received signal in terms of voltage and timing margin.

Constant Current Power Transmission Line-Based Power Delivery Network for Single-Ended Signaling

Existing digital automated test equipment (ATE) can provide signals at about 1 Gbps or slightly higher. To accommodate multi-GHz test needs, some ATE provide options for a few faster channels (up to 3.6 Gbps). However, leading-edge parts may require 100s of these signals and in some cases at even higher speeds (5 and 10 Gbps). This work describes a modular approach that allows for as many as 144 multiplexing and/or sampling channels to be added to existing ATE. The modules developed, so far include multiplexers, demultiplexers, and high-speed samplers that each support multiple high-speed differential signals. Production units operating up to 2.5 Gbps were introduced. We provide more detailed characterization of these modules and describe new modules targeting 3.2 Gbps and 5.0 Gbps applications. Various re-clocking techniques and proprietary calibration methods are used in order to reduce timing errors (especially jitter) to the sub-50ps range. The general system configuration, and key features of the newly developed modules are presented.

Modular extension of ATE to 5 Gbps

This paper describes a test application for an IC with over 200 logic signals each carrying multiple-gigahertz data. An aggregate data rate approaching a terabit-per-second is attained during the test. A high pin-count automated test system with a maximum frequency of 1.33 Gbps DNRZ is used as a development platform. Data rate tripling logic is added to the system to produce stimuli signals each with DNRZ rates up to 4 Gbps. High-speed sampling circuits are added to capture the device output signals at these same frequencies. Several example measurements illustrate the signal quality that is achieved. The extraordinary performance exhibited by this application represents one of the most challenging digital test applications reported to-date, and foreshadows expectations for future automated test equipment.

Terabit-per-second automated digital testing

A solution for testing fast-switching bidirectional signal lines using an array of technology-specific transceivers has been described previously (1998). This method uses an active component located between the device-under-test (DUT) and the automated test equipment (ATE) to reduce electrical interconnect delays to less than 150 ps. In this paper, the transceiver array concept is extended to include higher-level test processes such as real-time algorithmic pattern generation (APG), multi-gigahertz signal multiplexing, and others. The active test component is therefore called a "Test Support Processor" (TSP). It greatly reduces the functionality and performance capability required of the ATE, while maintaining signal integrity, and improving overall test quality. In its minimum configuration, the TSP provides an array of technology-specific transceivers very close to the DUT. This reduces transmission line effects, allowing for at-speed test of fast I/O switching characteristics. This technique may lead to lower-cost. The TSP is specifically intended to complement and support existing DFT and BIST structures within the DUT. The use of the TSP provides an additional degree of freedom for partitioning the test problem, and may result in a significant paradigm shift for future ATE architectures. This paper describes variations of the TSP concept, its potential applications, and economic impact. Three variations are illustrated through prototype demonstrations, including: (A) a 2.67 Gbps test pattern source, (B) a transceiver array for testing a high speed 4 Mbit SRAM, and (C) a reconfigurable real-time APG for memory testing, implemented using a field-programmable gate array (FPGA).

David Keezer

Papers

The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

Constant Current Power Transmission Line-Based Power Delivery Network for Single-Ended Signaling

Modular extension of ATE to 5 Gbps

Terabit-per-second automated digital testing

Test support processors for enhanced testability of high performance circuits