Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-/spl mu/m to 0.035-/spl mu/m feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.

The future of wires

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

/pdf/3-d-ics-a-novel-chip-design-for-improving-deep-submicrometer-6k9by1rs19.pdf

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

We assess climate impacts of global warming using ongoing observations and paleoclimate data. We use Earth's measured energy imbalance, paleoclimate data, and simple representations of the global carbon cycle and temperature to define emission reductions needed to stabilize climate and avoid potentially disas- trous impacts on today's young people, future genera- tions, and nature. A cumulative industrial-era limit of ,500 GtC fossil fuel emissions and 100 GtC storage in the biosphere and soil would keep climate close to the Holocene range to which humanity and other species are adapted. Cumulative emissions of ,1000 GtC, sometimes associated with 2uC global warming, would spur ''slow'' feedbacks and eventual warming of 3-4uC with disastrous consequences. Rapid emissions reduction is required to restore Earth's energy balance and avoid ocean heat uptake that would practically guarantee irreversible effects. Continuation of high fossil fuel emissions, given current knowledge of the consequences, would be an act of extraordinary witting intergenerational injustice. Re- sponsible policymaking requires a rising price on carbon emissions that would preclude emissions from most remaining coal and unconventional fossil fuels and phase down emissions from conventional fossil fuels.

/pdf/assessing-dangerous-climate-change-required-reduction-of-p1i679ogbk.pdf

Assessing "dangerous climate change": required reduction of carbon emissions to protect young people, future generations and nature.

Since the Justice and Development Party (AKP) came to power in 2002 Turkey has undergone double regime transitions. First, tutelary democracy ended; second, a competitive authoritarian regime has risen in its stead. We substantiate this assertion with specific and detailed evidence from 2015 election cycles, as well as from broader trends in Turkish politics. This evidence indeed confirms that elections are no longer fair; civil liberties are being systematically violated; and the playing field is highly skewed in favour of the ruling AKP. The June 2015 election results and their aftermath further confirm that Turkey has evolved into a competitive authoritarian regime.

/pdf/rising-competitive-authoritarianism-in-turkey-3ovpgz23jp.pdf

Rising competitive authoritarianism in Turkey

Even though rare earth metals are indispensible in modern technology, very little quantitative information other than combined rare earth oxide extraction is available on their life cycles. We have drawn upon published and unpublished information from China, Japan, the United States, and elsewhere to estimate flows into use and in-use stocks for 15 of the metals: La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y. Here, we show that the combined flows into use comprised about 90 Gg in 2007; the highest for individual metals were ∼28 Gg Ce and ∼22 Gg La, the lowest were ∼0.16 Gg Tm and ∼0.15 Gg Lu. In-use stocks ranged from 144 Gg Ce to 0.2 Gg Tm; these stocks, if efficiently recycled, could provide a valuable supplement to geological stocks.

Global in-use stocks of the rare Earth elements: a first estimate.

A 32 b 480 MHz PowerPC reduced-instruction-set-computer (RISC) microprocessor is migrated into an advanced 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors. These technology features have helped to increase the microprocessor internal clock frequency to 480 MHz at 2.0 V and 85/spl deg/C, and at the fast end of the process distribution. When operating at room temperature, the clock frequency increases to over 500 MHz. The microprocessor architecture includes two 32 KB L1 caches, one for data and one for instructions, integrated L2 cache controller working with L2 caches of 256 KB, 512 KB, or 1MB, and I/Os interfacing with the external bus using industry-standard 3.3 V. The microprocessor is implemented in 2.5 V CMOS technology and has migrated to 1.8 V CMOS technology.

A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects

Democracy in Crisis: Corruption, Media, and Power in Turkey

As the extent of the shortage becomes clear, an interagency task force is giving scientific users priority, but some say the material is not available at any price.

https://physicstoday.scitation.org/doi/pdf/10.1063/1.3455244

DOE begins rationing helium-3

A RISC microprocessor remapped in SOI technology exploits the advantages of SOI to boost processor frequency by 20% to 580MHz at 2.0V and 85/spl deg/C and fast process. The separation by implanted oxygen (SIMOX) SOI process produces partially-depleted devices. Source and drain capacitances are reduced by an order of magnitude, improving gate delay by 12%. Reduction in body-bias effects on device stacks and passgate topologies results in an additional 15%-25% improvement. Speed gains of up to 35% are achieved in some designs. The frequency-limiting paths in this processor are dominated by SRAM access and self-timed dynamic circuits whose timing had to be relaxed to guarantee functionality.

A 580 MHz RISC microprocessor in SOI

Demand for the elements is expected to surge in tandem with hybrid-electric vehicles, wind turbines, and other green technologies.

https://physicstoday.scitation.org/doi/pdf/10.1063/1.3431322

David Kramer

Papers

A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects

Democracy in Crisis: Corruption, Media, and Power in Turkey

DOE begins rationing helium-3

A 580 MHz RISC microprocessor in SOI

Concern grows over China’s dominance of rare-earth metals