David Levacq

Bio: David Levacq is an academic researcher from Université catholique de Louvain. The author has contributed to research in topics: Silicon on insulator & CMOS. The author has an hindex of 8, co-authored 18 publications receiving 410 citations.

Influence of device engineering on the analog and RF performances of SOI MOSFETs

Abstract: This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Composite ULP diode fabrication, modelling and applications in multi-V-th FD SOICMOS technology

Abstract: We present new SOI basic circuit cells architectures for ultra-low power (ULP) applications that use transistors in very weak inversion. These cells take advantage of the possibility to obtain multi-threshold transistors in fully depleted (FD) SOI CMOS with no additional cost. In particular, a new composite ULP diode is proposed and modelled. It has been fabricated on 0.18 and 2 mum FD SOI technologies and demonstrated a reduction of leakage currents by four orders of magnitude compared to standard MOS diode implementation. We demonstrate that the ULP diode can be used to realize memory cells that present strongly reduced static power consumption compared to standard SRAM cells and can work under 0.5 V supply voltage. As particular application, simulations of ULP memory latches used as level keepers in MTCMOS circuits to maintain information on floating nodes during standby mode demonstrate static power savings of 20% when compared to the best traditional schemes with comparable speed performance. Finally, measurements show that the new proposed ULP cells keep functionality at high temperature. (C) 2004 Elsevier Ltd. All rights reserved.

Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs

Abstract: This paper investigates the influence of the silicon substrate on the ac characteristics of silicon-on-insulator (SOI) MOSFETs. It is shown for the first time that the presence of the substrate underneath the buried oxide results in two transitions (i.e., zero-pole doublets) in the frequency response of the output conductance. It is demonstrated that the appearance of these transitions, the position and amplitude of which strongly depend on the substrate doping, is caused by the variation of the potential at substrate-buried oxide interface, which we call the Floating Effective Back-Gate (FEBG) effect. A first-order small-signal equivalent circuit is proposed to support our observations.

Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode

Abstract: A new CMOS digital storage device is developed based on the combination of two reverse biased composite CMOS diodes, each of them featuring ultra-low leakage and a negative impedance characteristic in reverse mode. The biasing of MOS transistors in very weak inversion, with negative gate-to-source voltages, results in a static current that lays orders of magnitude below that of conventional cross-coupled CMOS inverters. Based on our device, a 7-transistors SRAM cell is presented. Modeling, simulation and experimental characterization of the main properties of this cell are reported for a 0.13 mum partially-depleted SOI CMOS process. The feasibility of ultra-low leakage memory circuits is demonstrated experimentally by the design of a 256 times 1 bits SRAM column.

Intelligent SOI CMOS integrated circuits and sensors for heterogeneous environments and applications

Abstract: In this paper, we demonstrate how a simple fully-depleted SOI CMOS process can be adapted to provide a wide range of performance compatible with the realization of heterogeneous micropower, high-temperature or RF micro-systems which involve the integration of sensing, analog and digital components. High-temperature and low-voltage examples are discussed.

Review of Power Conditioning for Kinetic Energy Harvesting Systems

Abstract: In this paper, a summary of published techniques for power conditioning within energy harvesting systems is presented. The focus is on low-power systems, e.g, <;10 mW, for kinetic energy harvesting. Published concepts are grouped according to functionality and results contrasted. The various techniques described are considered in terms of complexity, efficiency, quiescent power consumption, startup behavior, and utilization of the harvester compared to an optimum load. This paper concludes with an overview of power management techniques that aim to maximize the extracted power and the utilization of the energy harvester.

Co-Design of a CMOS Rectifier and Small Loop Antenna for Highly Sensitive RF Energy Harvesters

Abstract: In this paper, a design method for the co-design and integration of a CMOS rectifier and small loop antenna is described. In order to improve the sensitivity, the antenna-rectifier interface is analyzed as it plays a crucial role in the co-design optimization. Subsequently, a 5-stage cross-connected differential rectifier with a 7-bit binary-weighted capacitor bank is designed and fabricated in standard 90 nm CMOS technology. The rectifier is brought at resonance with a high-Q loop antenna by means of a control loop that compensates for any variation at the antenna-rectifier interface and passively boosts the antenna voltage to enhance the sensitivity. A complementary MOS diode is proposed to improve the harvester's ability to store and hold energy over a long period of time during which there is insufficient power for rectification. The chip is ESD protected and integrated on a compact loop antenna. Measurements in an anechoic chamber at 868 MHz demonstrate a -27 dBm sensitivity for 1 V output across a capacitive load and 27 meter range for a 1.78 W RF source in an office corridor. The end-to-end power conversion efficiency equals 40% at -17 dBm.

Influence of device engineering on the analog and RF performances of SOI MOSFETs

Abstract: This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Influence of Channel and Gate Engineering on the Analog and RF Performance of DG MOSFETs

Abstract: The design of analog and RF circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep-submicrometer regime and emerging circuit applications. In this paper, we investigate the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications. The gate engineering technique used here is the dual-metal gate technology, and the channel engineering technique is the conventional halo doping process. For analog applications, importance is given to the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high-gain performances. Gate- and channel-engineered devices show an increase of gain by 45% and 35%, respectively, compared with the single-metal DG MOSFET. The gate-engineered device shows an improvement of 21.6% and 20% in the case of fT and fMAX values, whereas the channel-engineered device exhibits a reduction of fT by 2.7% with nearly equal fMAX.