Showing papers by "David W Parent published in 2009"
13 Nov 2009
TL;DR: A hardware version of the quadratic integrate and fire neural model, which differs from the more common integrate andFire neuron in that the model, and thus the hardware, intrinsically generate spikes.
Abstract: Silicon neurons are of importance both to implement hybrid electronic-biological system as well as to develop fundamental understanding of the neurobiological systems they emulate. We have implemented a hardware version of the quadratic integrate and fire neural model. The quadratic integrate and fire neuron differs from the more common integrate and fire neuron in that the model, and thus the hardware, intrinsically generate spikes. Readily available discrete surface mount components are used to make the hardware available to a wider audience and facilitate experimentation.
9 citations
25 Jul 2009
TL;DR: Improvements were implemented that included creating an online exam used for review and requiring earning a 70% or higher score on an in-class exam, a requirement for graduation.
Abstract: The San Jose State University Electrical Engineering (EE) department implemented a skill audit exam for graduating seniors in 1999 with the purpose of assessing the teaching and students' mastery of core concepts in EE. However, consistent low scores for the first years of the test suggested that students saw little incentive in reviewing or passing the test. To promote the concept that there is a set of basic skills every graduating senior should master, improvements were implemented that included creating an online exam used for review and requiring earning a 70% or higher score on an in-class exam, a requirement for graduation. After the improvements were made, all students demonstrated at least 70% mastery of the core EE concepts as measured by the improved, in-class skill audit exam. The details of these improvements are presented.
4 citations
13 Nov 2009
TL;DR: A design methodology is presented that uses 1-D process simulations of Metal Insulator Semiconductor (MIS) structures to design the threshold voltage of hafnium oxide based transistors used for neural recording.
Abstract: A design methodology is presented that uses 1-D process simulations of Metal Insulator Semiconductor (MIS) structures to design the threshold voltage of hafnium oxide based transistors used for neural recording. The methodology is comprised of 1-D analytical equations for threshold voltage specification, and doping profiles, and 1-D MIS Technical Computer Aided Design (TCAD) to design a process to implement a specific threshold voltage, which minimized simulation time. The process was then verified with a 2-D process/electrical TCAD simulation. Hafnium oxide films (HfO) were grown and characterized for dielectric constant and fixed oxide charge for various annealing temperatures, two important design variables in threshold voltage design.
2 citations