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Davide Bertozzi

Bio: Davide Bertozzi is an academic researcher from University of Ferrara. The author has contributed to research in topics: Network on a chip & Network topology. The author has an hindex of 18, co-authored 109 publications receiving 1071 citations.


Papers
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Journal ArticleDOI
TL;DR: A selected set of NoC-related research challenges are summarized with the hope to guide future development and trigger high-impact research progress.
Abstract: As multi-core systems transition to the many-core realm, the pressure on the interconnection network is substantially elevated. The Network-on-Chip (NoC) is expected to undertake the expanding demands of the ever-increasing numbers of processing elements, while--at the same time--technological and application constraints increase the pressure for increased performance and efficiency with limited resources. Although NoC research has evolved significantly the last decade, essential questions remain un-answered and call for fresh research ideas and innovative solutions. In this paper, we summarize a selected set of NoC-related research challenges, with the hope to guide future development and trigger high-impact research progress.

58 citations

Proceedings ArticleDOI
18 Mar 2013
TL;DR: A largely unexplored design point for asynchronous NoCs, relying on transition-signaling bundled data, which contributes to break the above barriers is proposed, and an existing lightweight synchronous switch architecture, xpipesLite is compared.
Abstract: Asynchronous networks-on-chip (NoCs) are an appealing solution to tackle the synchronization challenge in modern multicore systems through the implementation of a GALS paradigm. However, they have found only limited applicability so far due to two main reasons: the lack of proper design tool flows as well as their significant area footprint over their synchronous counterparts. This paper proposes a largely unexplored design point for asynchronous NoCs, relying on transition-signaling bundled data, which contributes to break the above barriers. Compared to an existing lightweight synchronous switch architecture, xpipesLite, the post-layout asynchronous switch achieved a 71% reduction in area, up to 85% reduction in overall power consumption, and a 44% average reduction in energy-per-flit, while mastering the more stringent timing assumptions of this solution with a semi-automated synthesis flow.

55 citations

Proceedings ArticleDOI
18 Mar 2013
TL;DR: This paper aims to go beyond the traditional comparison of wavelength-routed ONoC topologies based only on their abstract properties, and for the first time assesses their physical implementation efficiency in an homogeneous experimental setting of practical relevance.
Abstract: Optical networks-on-chip (ONoCs) are currently still in the concept stage, and would benefit from explorative studies capable of bridging the gap between abstract analysis frameworks and the constraints and challenges posed by the physical layer. This paper aims to go beyond the traditional comparison of wavelength-routed ONoC topologies based only on their abstract properties, and for the first time assesses their physical implementation efficiency in an homogeneous experimental setting of practical relevance. As a result, the paper can demonstrate the significant and different deviation of topology layouts from their logic schemes under the effect of placement constraints on the target system. This becomes then the preliminary step for the accurate characterization of technology-specific metrics such as the insertion loss critical path, and to derive the ultimate impact on power efficiency and feasibility of each design.

54 citations

Proceedings ArticleDOI
14 Mar 2011
TL;DR: This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC) that exploits the inherent structural redundancy of the NoC architecture in a cooperative way, thus detecting faults in test pattern generators too.
Abstract: This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC). Concurrent BIST operations are carried out after reset at each switch, thus resulting in scalable test application time with network size. The key principle consists of exploiting the inherent structural redundancy of the NoC architecture in a cooperative way, thus detecting faults in test pattern generators too. At-speed testing of stuck-at faults can be performed in less than 1200 cycles regardless of their size, with an hardware overhead of less than 11%.

53 citations

Journal ArticleDOI
TL;DR: ULBDR is presented, an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables, that requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories.
Abstract: The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables. uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the tradeoff between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the tradeoff between fault tolerance and performance. Power consumption, area, and delay estimates are also provided highlighting the efficiency of the mechanism. To do this, different router models (one for CMPs and one for MPSoCs) have been designed as a proof concept.

51 citations


Cited by
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Book
01 Jan 2012
Abstract: Experience and Educationis the best concise statement on education ever published by John Dewey, the man acknowledged to be the pre-eminent educational theorist of the twentieth century. Written more than two decades after Democracy and Education(Dewey's most comprehensive statement of his position in educational philosophy), this book demonstrates how Dewey reformulated his ideas as a result of his intervening experience with the progressive schools and in the light of the criticisms his theories had received. Analysing both "traditional" and "progressive" education, Dr. Dewey here insists that neither the old nor the new education is adequate and that each is miseducative because neither of them applies the principles of a carefully developed philosophy of experience. Many pages of this volume illustrate Dr. Dewey's ideas for a philosophy of experience and its relation to education. He particularly urges that all teachers and educators looking for a new movement in education should think in terms of the deeped and larger issues of education rather than in terms of some divisive "ism" about education, even such an "ism" as "progressivism." His philosophy, here expressed in its most essential, most readable form, predicates an American educational system that respects all sources of experience, on that offers a true learning situation that is both historical and social, both orderly and dynamic.

10,294 citations

Journal ArticleDOI
01 Apr 1988-Nature
TL;DR: In this paper, a sedimentological core and petrographic characterisation of samples from eleven boreholes from the Lower Carboniferous of Bowland Basin (Northwest England) is presented.
Abstract: Deposits of clastic carbonate-dominated (calciclastic) sedimentary slope systems in the rock record have been identified mostly as linearly-consistent carbonate apron deposits, even though most ancient clastic carbonate slope deposits fit the submarine fan systems better. Calciclastic submarine fans are consequently rarely described and are poorly understood. Subsequently, very little is known especially in mud-dominated calciclastic submarine fan systems. Presented in this study are a sedimentological core and petrographic characterisation of samples from eleven boreholes from the Lower Carboniferous of Bowland Basin (Northwest England) that reveals a >250 m thick calciturbidite complex deposited in a calciclastic submarine fan setting. Seven facies are recognised from core and thin section characterisation and are grouped into three carbonate turbidite sequences. They include: 1) Calciturbidites, comprising mostly of highto low-density, wavy-laminated bioclast-rich facies; 2) low-density densite mudstones which are characterised by planar laminated and unlaminated muddominated facies; and 3) Calcidebrites which are muddy or hyper-concentrated debrisflow deposits occurring as poorly-sorted, chaotic, mud-supported floatstones. These

9,929 citations

Book
26 Oct 2010
TL;DR: This issue contains three research papers and a comprehensive survey article on mobile ad hoc networks, describing the main characteristics of those networks and how they are being used, and discussing the most pressing issues and challenges associated with these temporary wireless networks.
Abstract: Welcome to the second installment of IJBDCN. This issue contains three research papers and a comprehensive survey article on mobile ad hoc networks. We would like to publish a couple of survey or tutorial articles per year as we believe this to be of value to our readers. Many research papers are necessarily focused and do not allow for a " panoramic " view of a particular subject. This is the gap that well-written survey or tutorial papers can fill. We are also planning a guest-edited special issue for the last quarter of this year and welcome your suggestions for future special issues of the journal. This second issue starts with a paper entitled " An Approach to Solving the Surviv-able Capacitated Network Design Problem " where Sridhar and Park studied the problem of selecting links of a network to construct primary and secondary routes for transfer of commodity traffic between nodes of the network. Their technique allows the design of survivable and cost-effective networks. In the second paper, " Query Processing Strategies for Location-Dependent Information Services " , Jayaputera and Taniar propose a new approach to generate a query result for location-dependent information services (LDIS). They argue that choosing a square as the scope of a query and dividing it into four equal regions, where a user is a center point of the scope, results in a faster searching time to find targets queried and brings a bigger chance to get rare targets. In addition, by avoiding resubmitting the same queries when the query results missed, the approach reduced bandwidth use at both the server and client sides. The third paper, " Addressing SPAM E-Mail Using Hashcash " by Curran and Honan tackles a problem experienced by most of us. The authors present the Hashcash proof-of-work approach and investigate the feasibility of implementing a solution based on that mechanism along with what they called a " cocktail " of antispam measures designed to keep junk mail under control. Finally , in the last paper, entitled " MANET: Applications, Issues, and Challenges for the Future " , Dhar presents an informative survey of mobile ad hoc networks, describing the main characteristics of those networks and how they are being used, and discussing the most pressing issues and challenges associated with these temporary wireless networks. We hope that you enjoy this and the upcoming issues of IJBDCN. Our goal is to …

262 citations

Proceedings Article
22 Feb 2016
TL;DR: A large-scale field study covering many millions of drive days, ten different drive models, different flash technologies, and no evidence that higher-end SLC drives are more reliable than MLC drives within typical drive lifetimes is provided.
Abstract: As solid state drives based on flash technology are becoming a staple for persistent data storage in data centers, it is important to understand their reliability characteristics. While there is a large body of work based on experiments with individual flash chips in a controlled lab environment under synthetic workloads, there is a dearth of information on their behavior in the field. This paper provides a large-scale field study covering many millions of drive days, ten different drive models, different flash technologies (MLC, eMLC, SLC) over 6 years of production use in Google's data centers. We study a wide range of reliability characteristics and come to a number of unexpected conclusions. For example, raw bit error rates (RBER) grow at a much slower rate with wearout than the exponential rate commonly assumed and, more importantly, they are not predictive of uncorrectable errors or other error modes. The widely used metric UBER (uncorrectable bit error rate) is not a meaningful metric, since we see no correlation between the number of reads and the number of uncorrectable errors. We see no evidence that higher-end SLC drives are more reliable than MLC drives within typical drive lifetimes. Comparing with traditional hard disk drives, flash drives have a significantly lower replacement rate in the field, however, they have a higher rate of uncorrectable errors.

239 citations

Journal ArticleDOI
TL;DR: The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years.
Abstract: Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. The most important results are summarized and open research problems and challenges are highlighted to guide future research on this topic.

198 citations