D
Davide Bertozzi
Researcher at University of Ferrara
Publications - 74
Citations - 4284
Davide Bertozzi is an academic researcher from University of Ferrara. The author has contributed to research in topics: Network on a chip & MPSoC. The author has an hindex of 29, co-authored 66 publications receiving 4181 citations. Previous affiliations of Davide Bertozzi include University of Bologna & Polytechnic University of Valencia.
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Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Journal ArticleDOI
Xpipes: a network-on-chip architecture for gigascale systems-on-chip
Davide Bertozzi,Luca Benini +1 more
TL;DR: An advanced NoC architecture, called Xpipes, targeting high performance and reliable communication for on-chip multi-processors is introduced, which consists of a library of soft macros that are design-time composable and tunable so that domain-specific heterogeneous architectures can be instantiated and synthesized.
Journal ArticleDOI
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
TL;DR: A complete simulation platform for a multi-processor systems-on-chip called MP-ARM is developed, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication architecture, memory models and support for parallel programming.
Journal ArticleDOI
Error control schemes for on-chip communication links: the energy-reliability tradeoff
TL;DR: Redundant bus coding is proved to be an effective technique for trading off energy against reliability, so that the most efficient scheme can be selected to meet predefined reliability requirements in a low signal-to-noise ratio regime.
Proceedings ArticleDOI
Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs
TL;DR: This paper proposes xpipes, a scalable and high-performance NoC architecture for multi-processor SoCs, consisting of soft macros that can be turned into instance-specific network components at instantiation time, to support both homogeneous and heterogeneous architectures.