Debasish Behera

Bio: Debasish Behera is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Flash ADC & Decimation. The author has an hindex of 4, co-authored 6 publications receiving 86 citations. Previous affiliations of Debasish Behera include Indian Institutes of Technology.

A 16 MHz BW 75 dB DR CT $\Delta\Sigma$ ADC Compensated for More Than One Cycle Excess Loop Delay

Abstract: The maximum sampling rate of a continuous-time ΔΣ modulator in a given process is limited by the minimum flash ADC delay that can be realized. Excess loop delay compensation techniques that are widely used can compensate for delays up to half a clock cycle. Addition of a fast loop outside the flash ADC can break this limit and compensate for one and half clock cycles of delay at the cost of reducing the order of noise shaping by one. This technique, along with a low latency flash ADC, and a delay free calibrated DAC, result in a lowpass continuous-time ΔΣ ADC with the highest reported sampling rate in a 0.18 m process. The prototype occupies 0.68 mm2 , consumes 47.6 mW, and operates at 800 MS/s. In a 16 MHz bandwidth (oversampling ratio of 25), the dynamic range, maximum signal to noise ratio, and maximum signal to noise and distortion ratios are 75 dB, 67 dB, and 65 dB respectively. In a 32 MHz bandwidth, the dynamic range, maximum signal to noise ratio, and maximum signal to noise and distortion ratios are 64 dB, 57 dB, and 57 dB, respectively.

A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay

Abstract: An 800MS/s CT ΔΣ ADC with 16MHz/32MHz bandwidths consumes 47.6mW from 1.8V and occupies 1mm2 in a 0.18µm CMOS process. The DR/SNR/SNDR for the two bandwidths are 75/67/65 dB and 64/57/57 dB respectively. Excess loop delay (ELD) of more than one cycle is compensated using a fast path outside the flash ADC. This and a low latency flash ADC and delay free DAC calibration result in the highest reported sampling rate in this process.

Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion

Abstract: This paper presents new techniques to obtain sample-by-sample analog-to-digital conversion using a delta–sigma modulator (DSM) without resetting the modulator or the decimation filter. It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist $M$ -band decimation filter running at the oversampled rate. It is also shown that a delta–sigma ADC preceded by a sample-and-hold at the Nyquist rate is a linear, time-invariant system at the Nyquist rate. This relaxes the constraint on the STF and allows using a multi-rate decimation filter and an equalizer at the Nyquist rate to significantly lower the power in the digital filters. Crosstalk suppression, which is limited by analog imperfections when a fixed-coefficient equalizer is used, is shown to be substantially improved using an adaptive equalizer at the Nyquist rate. A 180-nm prototype operating at 32 MHz and an OSR of 32 demonstrates two-channel operation with crosstalk below 89 dB. It consumes 18.2 mA from a 1.8-V supply, occupies 3.86 mm2 and has DR/SNR/SNDR of 84.2/82.5/80.1 dB.

A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter

Abstract: It is shown that memoryless analog-to-digital conversion using ΔΣ modulators is possible without resetting the modulator or decimation filters by using a suitable signal transfer function for the modulator and a decimation filter which satisfies Nyquist intersymbol interference (ISI) criterion. This architecture enables memoryless operation over the entire signal bandwidth of the ΔΣ modulator which is significantly higher than the bandwidth in incremental ΔΣ architectures in which the modulator is reset. A two-channel ADC with a total effective sampling rate of fs/64 per channel is built using a third order 32× oversampled switched-capacitor ΔΣ modulator. The prototype in 0.18 μm CMOS occupies 2.1 mm2 and consumes 59.63mW. At 16MHz (64MHz) sampling rate for the DSM, the dynamic range (DR) of the standalone modulator is 86.5 dB(85.1 dB), and that in two-channel mode, with perchannel rate of 250 kHz (1MHz) is 81 dB (80.5 dB). The maximum SNR in multiplexed mode at 16MHz (64MHz) sampling rate is 80.3 dB(68.6 dB). At both sampling rates, the inter-channel crosstalk due to maximum input on the other channel is below 77.7 dB.

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

Abstract: This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 $\mu{\rm m}$ CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 $\mu{\rm W}$ , which corresponds to a figure-of-merit of 0.85 pJ/conv.

A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback

Abstract: This paper presents the design of a continuous-time $\Delta\Sigma$ modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR, and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 ${\rm mm}^{2}$ and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

A Reconfigurable DT $\Delta \Sigma $ Modulator for Multi-Standard 2G/3G/4G Wireless Receivers

Abstract: The popularity of fourth generation (4G) cellular communication technology, and the concurrent predominance of second (2G) and third generation (3G) systems have made multi-standard wireless transceivers a necessity. This paper describes the system level planning, the architectural design, and the VLSI implementation of a reconfigurable discrete-time $\Delta \Sigma $ ADC for a multi-standard 2G/3G/4G wireless receiver. We present an optimized switched-capacitor loop filter implementation that maximizes the achievable sampling rate by deploying an early regeneration of the quantizer. Reconfigurability is mainly realized at the architectural level by adapting the oversampling ratio and the quantizer resolution, depending on the mode, to achieve the required dynamic range. Implemented in a 130 nm CMOS technology, and occupying an area of 0.31 ${\hbox {mm}}^{2}$ , the modulator runs at a maximum sampling rate of 450 MHz. The ADC achieves 87 dB and 63 dB DR in a 100 kHz and 25 MHz bandwidth, respectively. The effective resolution ranges from 13.2 bit to 9.7 bit at a scalable power consumption between 3.4 mW and 56.7 mW from a single 1.2 V supply. An open loop reference buffer is embedded on-chip to generate the required reference voltage levels (without the need for external components) making the modulator suitable for fully integrated cellular transceivers.

A 81-dB Dynamic Range 16-MHz Bandwidth $\Delta\Sigma$ Modulator Using Background Calibration

Abstract: A fourth-order discrete-time delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. It combines low-complexity circuits and digital calibrations to achieve high speed and high performance. The DSM is a cascade of two second-order loops. It has a sampling rate of 1.1 GHz and an input bandwidth of 16.67 MHz with an oversampling ratio of 33. It uses high-speed opamps with a dc gain of only 10. Two different types of digital calibrations are used. We first employ the integrator leakage calibration to correct the poles of the integrators. We then apply the noise leakage calibration to minimize the leaking quantization noise from the first loop. The noise leakage calibration also relaxes the component-matching requirements. Both calibrations can operate in the background without interrupting the normal DSM operation. The chip's measured signal-to-noise-and-distortion ratio and dynamic range are 74.32 and 81 dB, respectively. The chip consumes 94 mW from a 1 -V supply. The active area is 0.33 × 0.58 mm2.