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Debasri Saha

Bio: Debasri Saha is an academic researcher from Information Technology University. The author has contributed to research in topics: Hardware Trojan & Quantum algorithm. The author has an hindex of 9, co-authored 58 publications receiving 238 citations. Previous affiliations of Debasri Saha include University of Calcutta & Indian Statistical Institute.


Papers
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Journal ArticleDOI
TL;DR: This work establishes that Verify_ZKP satisfies zero-knowledge property, and introduces statistical metrics to measure its robustness and overhead, and has simulated the protocol for IWLS'05 FPGA benchmarks.
Abstract: In nanometer technology regime, design components mandate their reuse to meet the complex design challenges and hence comprise Intellectual Property (IP). Unauthorized reuse raises major security issues. IP mark(s) is embedded into a design for establishing the veracity of a legal IP owner/buyer. However, methods for trustworthy public verification of IP marks are not secure. For field-programmable gate-array (FPGA) designs, marks become prone to tampering, and even being overridden by an attacker's signature after public verification. In order to ensure trustworthy yet leakage-proof public verification based on the marks hidden in a FPGA design, we propose a zero-knowledge protocol Verify_ZKP. It is an interactive two-person game between the prover and the verifier. This protocol is fast, incurs no additional design overhead, and needs no centralized signature database. We establish that Verify_ZKP satisfies zero-knowledge property, and introduce statistical metrics to measure its robustness. We have simulated our protocol for IWLS'05 FPGA benchmarks. Experimental results on robustness and overhead are very encouraging.

33 citations

Proceedings ArticleDOI
17 Dec 2007
TL;DR: The proposed algorithm ROBUST-IP facilitates faster extraction of signatures of IP owner and buyer, whereas removing or tampering the watermarks by an attacker remains infeasible, even if public verification is allowed.
Abstract: In deep sub-micron VLSI technology, design reuse has become essential due to more integration on a single chip in shorter time. Design reuse however is susceptible to misappropriation of the intellectual property (IP) of the design. There may be illegal reselling or unauthorized reuse of the design, creating false charges on legal buyer by the IP owner, false claim for IP ownership, tampering of watermarks present in the design for IP protection (IPP). While identifying IP owner and legal IP buyer through copy detection remains an exhaustive method, public and convincing watermark verification for IP ownership is not still safe. Our proposed algorithm ROBUST-IP tackles all the problems from an entirely new viewpoint. It facilitates faster extraction of signatures of IP owner and buyer, whereas removing or tampering the watermarks by an attacker remains infeasible, even if public verification is allowed. The scheme is effectively applied for IPP in both ASIC and FPGA designs. It has been tested on various MCNC benchmarks. The experimental results are quite encouraging and the overhead incurred by our technique on the design is negligible.

28 citations

Journal ArticleDOI
TL;DR: The IP-based SoC design flow is discussed to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringement.
Abstract: Increased design complexity, shrinking design cycle, and low cost--this three-dimensional demandmandates advent of system-onchip (SoC) methodology in semiconductor industry. The key concept of SoC is reuse of the intellectual property (IP) cores. Reuse of IPs on SoC increases the risk of misappropriation of IPs due to introduction of several new attacks and involvement of various parties as adversaries. Existing literature has huge number of proposals for IP protection (IPP) techniques to be incorporated in the IP design flow as well as in the SoC design methodology. However, these are quite scattered, limited in possibilities in multithreat environment, and sometimes mutually conflicting. Existing works need critical survey, proper categorization, and summarization to focus on the inherent tradeoff, existing security holes, and new research directions. This paper discusses the IP-based SoC design flow to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringements. It also clearly highlights recent challenges and new opportunities in this emerging field of research.

21 citations

Proceedings ArticleDOI
01 Jan 2017
TL;DR: This work proposes a self aware approach which works on the observe-decide-act (ODA) paradigm to counteract the effects of Trojans, which may induce sudden unintentional delays at runtime, affecting the basic security principles of the SoC.
Abstract: A major issue of present age system on chip (SoC) designing is meeting of stringent time to market deadlines along with the reduction of various challenges faced during design. A significant strategy adopted in tackling such a problem is to procure different components or IPs (intellectual properties) of the SoC from different third party IP vendors (3PIPs). Such a technique targets independent working of the SoC components and removes the threat of the occurrence of malicious circuitry or Hardware Trojan Horse (HTH) having a distributed architecture. However, trustworthiness of the 3PIP vendors is a concern and possibility exists in the implantation of a HTH in the individual IPs procured from them. In this work, we analyze the effects of such Trojans, which may induce sudden unintentional delays at runtime, affecting the basic security principles of the SoC. We propose a self aware approach which works on the observe-decide-act (ODA) paradigm to counteract the scenario. Existing literature on hardware security generally focus on detection of anomaly, but is silent on organizing low level security mechanisms in such a manner that the high level objective of secure task completion is facilitated at run time. Our proposed methodology not only overcomes this limitation but also ensures security without tampering the IP designs. Experimental analysis is performed using AES crypto SoC architecture. Low overhead in area and power of the security elements as obtained in experimentation supports its applicability for practical SoC applications.

17 citations

Proceedings ArticleDOI
03 Jan 2010
TL;DR: A novel scheme to watermark the recent reconfigurable scan architectures, operating in both scan tree and single scan mode, is proposed and Experimental results on design overhead and robustness for ISCAS’89 benchmarks are encouraging.
Abstract: IP values contributed by the distinct design tools in specific design phases, are recognized by observing the signature of the owner of each tool as functional or scan mode output of the fabricated chip, for certain input vector secret to the owner. An existing approach inserts watermark through reordering of single scan chain, and solely identifies the owner of the logic design tool. Here we propose a novel scheme to watermark the recent reconfigurable scan architectures, operating in both scan tree and single scan mode. The signature of the owner of physical design tool along with that of logic design tool can separately be embedded while designing the scan tree and also verified from the packaged chip without conflict using two distinct modes. A bi-objective minimization of overhead in routing and power is supported through our scheme. Experimental results on design overhead and robustness for ISCAS’89 benchmarks are encouraging.

16 citations


Cited by
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01 Jan 1992
TL;DR: In this paper, the Voronoi diagram generalizations of the Voroni diagram algorithm for computing poisson Voroni diagrams are defined and basic properties of the generalization of Voroni's algorithm are discussed.
Abstract: Definitions and basic properties of the Voronoi diagram generalizations of the Voronoi diagram algorithms for computing Voronoi diagrams poisson Voronoi diagrams spatial interpolation models of spatial processes point pattern analysis locational optimization through Voronoi diagrams.

133 citations

Journal ArticleDOI
TL;DR: A fast deep-reinforcement-learning (DRL)-based detection algorithm for virtual IP watermarks is proposed by combining the technologies of mapping function and DRL to preprocess the ownership information of the IP circuit resource.
Abstract: With the fast advancements of electronic chip technologies in the Internet of Things (IoT), it is urgent to address the copyright protection issue of intellectual property (IP) circuit resources of the electronic devices in IoT environments. In this article, a fast deep-reinforcement-learning (DRL)-based detection algorithm for virtual IP watermarks is proposed by combining the technologies of mapping function and DRL to preprocess the ownership information of the IP circuit resource. The deep $Q$ -learning (DQN) algorithm is used to generate the watermarked positions adaptively, making the watermarked positions secure yet close to the original design, turning the watermarked positions secure. An artificial neural network (ANN) algorithm is utilized for training the position distance characteristic vectors of the IP circuit, in which the characteristic function of the virtual position for IP watermark is generated after training. In IP ownership verification, the DRL model can quickly locate the range of virtual watermark positions. With the characteristic values of the virtual positions in each lookup table (LUT) area and surrounding areas, the mapping position relationship can be calculated in a supervised manner in the neural network, as the algorithm realizes the fast location of the real ownership information in an IP circuit. The experimental results show that the proposed algorithm can effectively improve the speed of watermark detection as also reducing the resource overhead. Besides, it also achieves excellent performance in security.

129 citations

Journal ArticleDOI
TL;DR: In this article, the authors provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture.
Abstract: The remarkable success of machine learning (ML) in a variety of research domains has inspired academic and industrial communities to explore its potential to address hardware Trojan (HT) attacks. While numerous works have been published over the past decade, few survey papers, to the best of our knowledge, have systematically reviewed the achievements and analyzed the remaining challenges in this area. To fill this gap, this article surveys ML-based approaches against HT attacks available in the literature. In particular, we first provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture. Based on the review, we further discuss the lessons learned in and challenges arising from previous studies. Despite current work focusing more on chip-layer HT problems, it is notable that novel HT threats are constantly emerging and have evolved beyond chips and to the component, device, and even behavior layers, therein compromising the security and trustworthiness of the overall hardware ecosystem. Therefore, we divide the HT threats into four layers and propose a hardware Trojan defense (HTD) reference model from the perspective of the overall hardware ecosystem, therein categorizing the security threats and requirements in each layer to provide a guideline for future research in this direction.

90 citations

Book
01 Aug 2004
TL;DR: A vital tool for professional engineers, as well as graduate students of engineering, the text explains the design issues, guidelines, and CAD tools for the power distribution of the VLSI chip and package, and provides numerous examples for its effective application.
Abstract: Description: A hands-on troubleshooting guide for VLSI network designers The primary goal in VLSI (very large scale integration) power network design is to provide enough power lines across a chip to reduce voltage drops from the power pads to the center of the chip. Voltage drops caused by the power network's metal lines coupled with transistor switching currents on the chip cause power supply noises that can affect circuit timing and performance, thus providing a constant challenge for designers of high-performance chips. Power Distribution Network Design for VLSI provides detailed information on this critical component of circuit design and physical integration for high-speed chips. A vital tool for professional engineers (especially those involved in the use of commercial tools), as well as graduate students of engineering, the text explains the design issues, guidelines, and CAD tools for the power distribution of the VLSI chip and package, and provides numerous examples for its effective application. Features of the text include: An introduction to power distribution network design Design perspectives, such as power network planning, layout specifications, decoupling capacitance insertion, modeling, and analysis Electromigration phenomena IR drop analysis methodology Commands and user interfaces of the VoltageStorm(TM) CAD tool Microprocessor design examples using on-chip power distribution Flip-chip and package design issues Power network measurement techniques from real silicon The author includes several case studies and a glossary of key words and basic terms to help readers understand and integrate basic concepts in VLSI design and power distribution.

83 citations