Deepak C. Sekar

TL;DR: In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.

TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.

TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.

TL;DR: In this paper, the authors consider a device including a first layer of first transistors interconnected by at least one first interconnection layer, wherein the first interconnect layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first Interconnect layer, and a connection path connecting one of the second transistor to the firstInterconnect layer.

TL;DR: In this paper, a 3D IC based system including a first semiconductor layer including first alignment marks and first transistors, wherein the first transistor are interconnected by at least one metal layer including aluminum or copper, is presented.