Deleep R. Nair

Bio: Deleep R. Nair is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Metal gate & Leakage (electronics). The author has an hindex of 12, co-authored 62 publications receiving 632 citations. Previous affiliations of Deleep R. Nair include Indian Institutes of Technology & Indian Institute of Technology Bombay.

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

Abstract: For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Abstract: Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

32nm general purpose bulk CMOS technology for high performance applications at low voltage

Abstract: This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (AVT~2.8 mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent static noise margin (SNM) of 213 mV has been achieved at low voltage for a high density 0.157 um2 SRAM cell. Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125degC.

Scaling of 32nm low power SRAM with high-K metal gate

Abstract: This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG Tinv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum2 cell to meet low power application requirements.

Competitive and cost effective high-k based 28nm CMOS technology for low power applications

Abstract: In this paper, we present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm2, and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28nm from 45nm technology. Our high-density SRAM bit-cell (area= 0.120mm2) has a demonstrated Static Noise Margin (SNM) of 213mV at 1V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28nm LP poly/SiON reference [3]. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT∼2mV.um) versus our previously-reported result [2]. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k∼2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Contact Structure of Semiconductor Device

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

Process Technology Variation

Abstract: Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications

Abstract: 22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μΑ/μm (856μΑ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V V min for 8T logic libraries, as well as 0.62V and 0.52V V min for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm I off , and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high f T /f MAx of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high f MAx extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.