Deleep R. Nair

Bio: Deleep R. Nair is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Metal gate & Leakage (electronics). The author has an hindex of 12, co-authored 62 publications receiving 632 citations. Previous affiliations of Deleep R. Nair include Indian Institutes of Technology & Indian Institute of Technology Bombay.

Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters

Abstract: The origin of drain disturb in NOR Flash EEPROM cells under channel initiated secondary electron (CHISEL) programming operation is identified. A comparative study of drain disturb under channel hot electron (CHE) and CHISEL operation is performed as a function of drain bias and temperature on bitcells having different floating gate length and junction depth. The disturb mechanism is shown to originate from band-to-band tunneling under CHISEL operation, unlike that under CHE operation that originates from source-drain leakage. The effect of technological parameters (channel doping and drain junction depth) on CHISEL drain disturb is studied for both the charge gain (erased cell) and charge loss (programmed cell) disturb modes. Fullband Monte Carlo device simulations are used to explain the experimental results. It is shown that methods for improving CHISEL programming performance (higher channel doping and/or lower drain junction depth or halo) increase drain disturb, which has to be carefully considered for efficient design of scaled cells.

Asymmetric channel MOSFET

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Piezoelectric-on-Silicon Array Resonators With Asymmetric Phononic Crystal Tethering

Abstract: The design, fabrication, and characterization of Piezoelectric-on-Silicon array resonators with asymmetric Phononic crystal (PnC) tethering for applications in high frequency reference oscillators is presented. A hybrid approach of mechanical arraying along with higher mode of operation is used for minimizing the motional resistance. For improving the Q-factor, novel asymmetric PnC tethers are developed that not only exhibit a larger bandgap than their symmetric PnC counterparts, but also have significantly better design optimization capabilities for fine tuning the tether properties. Third order longitudinal mode resonators operating at frequencies of ~300 MHz with and without PnC tethering and with different number of resonators in the array were fabricated using $2~\mu \text{m}$ SOI wafers. The measured characteristics of the resonators showed a peak unloaded Q-factor of 4454 and a motional resistance of 200 $\Omega $ at 312 MHz for a seven resonator array. These results are comparable with the best reported in literature, in spite of a lesser silicon thickness. [2016-0194]

CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters

Abstract: The impact of programming biases, device scaling and variation of technological parameters on channel initiated secondary electron (CHISEL) programming performance of scaled NOR Flash electrically erasable programmable read-only memories (EEPROMs) is studied in detail. It is shown that CHISEL operation offers faster programming for all bias conditions and remains highly efficient at lower biases compared to conventional channel hot electron (CHE) operation. The physical mechanism responsible for this behavior is explained using full band Monte Carlo simulations. CHISEL programming efficiency is shown to degrade with device scaling, and various technological parameter optimization schemes required for its improvement are explored. The resulting increase in drain disturbs is also studied and the impact of technological parameter optimization on the programming performance versus drain disturb tradeoff is analyzed. It is shown that by judicious choice of technological parameters the advantage of CHISEL programming can be maintained for deeply scaled electrically erasable programmable read-only memory (EEPROM) cells.

A Scalable, Broadband, and Physics-Based Model for On-Chip Rectangular Spiral Inductors

Abstract: A scalable, broadband, and physics-based compact model for on-chip spiral inductors with rectangular outline shape is demonstrated for the first time in this paper. A simple dc inductance model is developed based on the current sheet approximation. The reduction in inductance due to the flow of eddy current in a back metal plate is considered using the method of images. A three-ladder network is shown to be sufficient to accurately model skin effect caused due to the magnetic field setup at high frequencies. Geometry-dependent expression suitable for rectangular cross-sectional metal strips is presented to predict the proximity effect. Physics-based expression for the substrate capacitance is derived. The proposed model is also shown to have a good correlation in the presence of a patterned ground shield. The proposed model is verified across CMOS process parameters that affect the inductor performance, such as metal thickness, substrate resistivity, and substrate thickness. Furthermore, model accuracy is also validated across design parameters such as spiral width, spacing between turns, number of turns, and diameter. The model is shown to have a good agreement with both EM simulations and measurements.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Contact Structure of Semiconductor Device

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

Process Technology Variation

Abstract: Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications

Abstract: 22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μΑ/μm (856μΑ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V V min for 8T logic libraries, as well as 0.62V and 0.52V V min for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm I off , and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high f T /f MAx of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high f MAx extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.