Deleep R. Nair

Bio: Deleep R. Nair is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Metal gate & Leakage (electronics). The author has an hindex of 12, co-authored 62 publications receiving 632 citations. Previous affiliations of Deleep R. Nair include Indian Institutes of Technology & Indian Institute of Technology Bombay.

Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation

Abstract: The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in source/drain leakage, reduction in band-to-band tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.

Impact of Source to Drain Tunneling on the Ballistic Performance of Si, Ge, GaSb, and GeSn Nanowire p-MOSFETs

Abstract: We investigated the effect of material choice and orientation in limiting source to drain tunneling (SDT) in nanowire (NW) p-MOSFETs. Si, Ge, GaSb, and Ge 0.96 Sn 0.04 nanowire MOSFETs (NWFETs) were simulated at a scaled gate length (L G ) of 10 nm, using rigorous ballistic quantum transport simulations. To properly account for the non-parabolicity and anisotropy of the valence band, the k·p method was used. For each material, we simulated a set of six different transport/confinement directions, at a fixed OFF-state current (I OFF ) of 100 nA/μm and supply voltage V DD = -0.5 V to identify the direction with the highest ON-current (I ON ). For Ge, GaSb, and GeSn [001]/110/110 oriented NWFETs, with [001] being the direction of transport and 110, 110 being the directions of confinement for the nanowire, showed the best ON-state performance, compared to other orientations. Our simulation results show that, despite having a higher percentage of SDT in OFF-state than silicon, GaSb [001]/110/110 NWFET can outperform Si NWFETs. We further examined the role of doping in limiting SDT and demonstrated that the ON-state performance of Ge and GeSn NWFETs could be improved by reducing the doping in the source/drain (S/D) extension regions. Our simulation result show that with properly chosen channel transport orientation and S/D doping concentration, performance of materials with high hole mobility can be optimized to reduce the impact of SDT and provide a performance improvement over Si-channel based p-MOSFETs.

Design and Fabrication of Reliable Power Efficient Bistable MEMS Switch Using Single Mask Process

Abstract: A bistable DC switch based on buckled beams and thermal actuation has been designed, fabricated and characterised. The buckled beams, which require very low actuation force and provide a sufficiently large contact force, are designed based on a parametric study. U-shaped thermal actuators are designed to provide the actuation force with minimum electrical power. The compact switch is fabricated using a simple single mask process on a SOI wafer. The average switching power is measured to be 60 $mW$ , while the average switching delay is 350 ${\mu }s$ . The power-delay product of about $20~{\mu }J$ is the lowest reported so far for bistable MEMS switches based on thermal actuation. The switch retains functionality even after 5 million switching cycles. [2020-0026]

Mechanism of drain disturb in SONOS flash EEPROMs

Abstract: We investigate the mechanism of drain disturb in SONOS flash memory cells. Our results show that drain disturb can be a serious concern in a programmed state and is caused by injection of holes from the substrate into the nitride. We identify the key factors responsible for this to be band-to-band tunneling at the drain junction and impact ionization of the channel leakage current.

1D and 2D wide acoustic bandgap Phononic Crystal structures for performance improvement of AlN-on-Si resonators operating in GHz range

Abstract: Design and simulation of Phononic Crystals (PnCs) with a wide Acoustic Band Gap (ABG) around 1 GHz is presented. A new PnC unit cell topology is designed, which has a very wide ABG of 138 MHz with center frequency around 1 GHz and minimum feature size of 0.6 μm. Wider ABG allows better enhancement of the Quality factor (Q) by reducing the anchor loss. Effect of geometrical variation and the periodicity of PnC are discussed. ABG for 1D and 2D periodicity is simulated and geometrical dimensions to obtain similar ABG in both cases are compared.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Contact Structure of Semiconductor Device

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

Process Technology Variation

Abstract: Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications

Abstract: 22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μΑ/μm (856μΑ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V V min for 8T logic libraries, as well as 0.62V and 0.52V V min for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm I off , and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high f T /f MAx of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high f MAx extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.