Derryl Allman

Bio: Derryl Allman is an academic researcher from ON Semiconductor. The author has contributed to research in topics: Stress migration & Layer (electronics). The author has an hindex of 6, co-authored 24 publications receiving 114 citations. Previous affiliations of Derryl Allman include Avago Technologies.

Atomic Layer Deposition of Ruthenium and Ruthenium Oxide Using a Zero-Oxidation State Precursor

Abstract: Atomic layer deposition (ALD) processes are reported for ruthenium (Ru) and ruthenium oxide (RuO2) using a zero-oxidation state liquid precursor, η4-2,3-dimethylbutadiene ruthenium tricarbonyl [Ru(DMBD)(CO)3]. Both ALD Ru and RuO2 films were deposited using alternating N2 -purge-separated pulses of Ru(DMBD)(CO)3 and O2. ALD Ru metal films were deposited via short (2 s) pulses of O2. Ru films have an ALD temperature window from 290 to 320 °C with a GPC of 0.067 nm/cycle and a negligible nucleation delay on SiO2. Ru films show a strong hexagonal crystal structure with low resistivity of approximately 14 μΩ cm at 320 °C. RuO2 films were deposited using longer (20 s) pulses of either molecular O2 or O2 plasma. RuO2 films deposited via thermal ALD using molecular O2 have a temperature window from 220 to 240 °C with a GPC and nucleation delay on SiO2 of 0.065 nm/cycle and 35 cycles, respectively. Thermal ALD RuO2 films show a distinct rutile phase microstructure with a resistivity of approximately 62 μΩ cm. In ...

Impact of via interactions and metal slotting on stress induced voiding

Abstract: Stress induced voiding was investigated for a 0.13 mum Cu/low-k interconnect process. The focus of our study was on the ldquohumprdquo failure mode using a statistical approach to both the design of the vehicle and the data analysis. The time-to-failure (TTF) was studied with respect to geometrical aspects of the lower metal level, insertion of a dummy via, via arrays and metal slotting for long via chains. It is found that insertion of dummy vias increased the reliability, through reduction in the probability for void nucleation and a reduction in void growth rate. The lifetime improvement is attributed to a stress modification in the interconnect. The stress modification can effect vias far from the local ldquodiffusive volumerdquo during void growth, indicating possible new approaches for redundant electrical or dummy via placement. Insertion of metal slots close to the electrically active via act as a diffusive barrier, and slots located elsewhere can modify the stress in the interconnect to improve via lifetime.

Plasma Enhanced Atomic Layer Deposition of Al 2 O 3 /SiO 2 MIM Capacitors

Abstract: Metal–insulator–insulator–metal (MIIM) capacitors with bilayers of Al2O3 and SiO2 are deposited at 200 °C via plasma enhanced atomic layer deposition. Employing the cancelling effect between the positive quadratic voltage coefficient of capacitance ( $\alpha $ VCC) of Al2O3 and the negative $\alpha $ VCC of SiO2, devices are made that simultaneously meet the International Technology Roadmap for Semiconductors 2020 projections for capacitance density, leakage current density, and voltage nonlinearity. Optimized bilayer Al2O3/SiO2 MIIM capacitors exhibit a capacitance density of 10.1 fF/ $\mu \text{m}^{2}$ , a leakage current density of 6.8 nA/cm $^{2}$ at 1 V, and a minimized $\alpha $ VCC of −20 ppm/ $\text{V}^{2}$ .

Atomic layer deposition of bismuth oxide using Bi(OCMe2iPr)3 and H2O

Abstract: Bismuth oxide thin films were deposited by atomic layer deposition using Bi(OCMe2iPr)3 and H2O at deposition temperatures between 90 and 270 °C on Si3N4, TaN, and TiN substrates. Films were analyzed using spectroscopic ellipsometry, x-ray diffraction, x-ray reflectivity, high-resolution transmission electron microscopy, and Rutherford backscattering spectrometry. Bi2O3 films deposited at 150 °C have a linear growth per cycle of 0.039 nm/cycle, density of 8.3 g/cm3, band gap of approximately 2.9 eV, low carbon content, and show the β phase structure with a (201) preferred crystal orientation. Deposition temperatures above 210 °C and postdeposition anneals caused uneven volumetric expansion, resulting in a decrease in film density, increased interfacial roughness, and degraded optical properties.

Method for manufacturing an energy storage device and structure therefor

Abstract: An energy storage device such as a metal-insulator-metal capacitor and a method for manufacturing the energy storage device. The metal-insulator-metal capacitor includes an insulating material positioned between a bottom electrode or bottom plate and a top electrode or top plate. The surface area of the bottom electrode is greater than the surface area of the insulating material and the surface area of the insulating material is greater than the surface area of the top electrode. The top electrode and the insulating layer have edges that are laterally within and spaced apart from edges of the bottom electrode. A protective layer covers the top electrode, the edges of the top electrode, and the portions of the insulating layer that are uncovered by the top electrode. The protective layer serves as an etch mask during the formation of the bottom electrode.

Kinetics Of Materials

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Dummy Pattern Design for Reducing Device Performance Drift

Abstract: A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.

Atomic layer deposition of metals: Precursors and film growth

Abstract: The coating of complex three-dimensional structures with ultrathin metal films is of great interest for current technical applications, particularly in microelectronics, as well as for basic research on, for example, photonics or spintronics. While atomic layer deposition (ALD) has become a well-established fabrication method for thin oxide films on such geometries, attempts to develop ALD processes for elemental metal films have met with only mixed success. This can be understood by the lack of suitable precursors for many metals, the difficulty in reducing the metal cations to the metallic state, and the nature of metals as such, in particular their tendency to agglomerate to isolated islands. In this review, we will discuss these three challenges in detail for the example of Cu, for which ALD has been studied extensively due to its importance for microelectronic fabrication processes. Moreover, we give a comprehensive overview over metal ALD, ranging from a short summary of the early research on the ALD of the platinoid metals, which has meanwhile become an established technology, to very recent developments that target the ALD of electropositive metals. Finally, we discuss the most important applications of metal ALD.