Dheeraj Kumar Sinha

Bio: Dheeraj Kumar Sinha is an academic researcher from Indian Institute of Technology Guwahati. The author has contributed to research in topics: Field-effect transistor & Transistor. The author has an hindex of 2, co-authored 10 publications receiving 21 citations. Previous affiliations of Dheeraj Kumar Sinha include Indian Institutes of Information Technology.

2-D Analytical Modeling of Surface Potential and Threshold Voltage for Vertical Super-Thin Body FET

Abstract: In this paper, a 2-D analytical model for surface potential and threshold voltage of novel vertical super-thin body (VSTB) FET has been derived by solving 2-D Poisson equation. The analytical surface potential expression for gate-side surface and sidewall side surface has been modeled using parabolic surface potential approximation. The threshold voltage model for the VSTB FET has been derived by applying strong inversion criterion at the surface potential minimum value. The threshold voltage model for the VSTB FET has been analyzed by varying the body thickness, oxide thickness, and channel doping concentrations. The drain-induced barrier lowering and threshold voltage roll-off parameters are also extracted and analyzed for different body thicknesses. The models for surface potential and threshold voltage have been compared with the results obtained from the 2-D numerical device simulator and a very good agreement between the two has been observed.

Modeling Erratic Behavior Due to High Current Filamentation in Bipolar Structures Under Dynamic Avalanche Conditions

Abstract: This paper models the indeterminacy that occurs during the formation of breakdown current channels in a bipolar structure, when subjected to an ultrafast high voltage pulse. The experimental results, pertaining to different regimes of the voltage ramp speed, applied across the bipolar structure are modeled. The avalanche injection mechanisms under variable high speed ramps are studied through the formation and propagation of ionizing waves, which lead to either weak or strong injection of mobile carriers, as the high current injection paths get coupled. Furthermore, the role of emitter injection is related to the indeterminacy associated with the snapback phenomenon and systematically related to the experimental observations.

A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach

Abstract: This work explores the new ESD (electrostatic discharge) protection design methodology for high speed off-chip communication ICs (Integrated Circuits). We propose novel methodology which describes the optimized design prediction of ESD protection device under HBM (Human Body Model) stress condition. Furthermore, we have discussed the ESD-I/O circuit interaction and improved the ESD circuit robustness by varying the various layout parameters and minimizing the parasitic capacitance of the protection device. Here, GG-NMOS (Gate Grounded NMOS) is taken as an ESD protection device. Moreover, LVDS (Low Voltage Differential Signaling) driver circuit is used as test circuit, where we compared the impact of capacitance due to protection device on circuit performance. The second breakdown triggering current (It2) which can be considered a metric of ESD robustness, is dependent on the drain to gate contact spacing (DCGS). We show that spacing optimization effectively elevates It2 by increasing the ballasting behavior and uniformity in current distribution while causing only a marginal increment in parasitic capacitance.

A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET

Abstract: This paper presents novel capacitor less dynamic random access memory (DRAM) cells through band-gap engineered silicon-germanium (SiGe) junction less double gate field effect transistor (JL-DGFET) using two-dimensional commercial TCAD device simulator. The design window of capacitor less DRAM cell and its operations have been described. We observe hysteresis current-voltage characteristic and steep change in sub-threshold slope (SS) in SiGe JL-DGFET. The correlation between the IDS -- VGS and IDS -- VDS characteristics of the device during different operation of memory cells are discussed. Furthermore, high value of bipolar gain (i.e. s) is observed in optimally designed SiGe JL-DGFET transistors, which can be utilized for the improvement of sensing margin in dynamic memories. The results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology.

Methodology for optimizing ESD protection for high speed LVDS based I/Os

Abstract: This work explores a methodology to optimize the layout of a electro-static discharge (ESD) structures for improving the performance of low voltage swing differential amplifier (LVDS). The parasitic capacitance of ESD structures are extracted. The role of our work is to optimize the parasitic capacitance in the I/O circuit while improving the ESD robustness. The work first compares impact of capacitance in LVDS swing behaviour and it has been observed that there is a sharp fall due to charging time constant. As ESD robustness improves by increasing the ballasting behaviour while marginal increase in capacitance, there is a much better improvement in width scaling down leads to much reduction in capacitance and thus I/O circuit improvement.

Performance analysis of vertical super-thin body (VSTB) FET and its characteristics in presence of noise

Abstract: In this work, a simulation-based performance study of vertical super-thin body (VSTB) MOSFET vis-a-vis various other MOS devices was presented. Use of appropriate doping profile greatly improves on to off current ratio (ION/IOFF) and subthreshold swing (SS). Improvement in input characteristics (ID–VGS) by gate–source (G/S) and gate–drain (G/D) overlap technique was explained with the help of electron density, mobility, and velocity of the device in off and on-states. Device performance shows negligible deviations in presence of different effects like stress, strain, tunneling, and velocity saturation. VSTB FET supports the downscaling of device size by offering excellent electrostatic integrity and low supply voltage operation. Values of off-current (IOFF), peak on-current (ION), peak transconductance (gm), SS, and DIBL for channel length (L) of 20 nm are 0.00145 nA/µm, 327.85 µA/µm, 974 µS/µm, 65.1 mV/dec, and 39.6 mV/V, respectively. Noise impact on device performance for three different noise sources (diffusion, generation–recombination/G–R, and flicker noise) was studied at two different frequencies (f = 1 MHz and 10 GHz). Maximum values of unit-gain cut-off frequencies (fTmax) obtained for channel lengths (L) of 20, 25, and 30 nm are 86.26, 80.47, and 76.22 GHz, respectively.

Power Electronic Pulse Generators for Water Treatment Application: A Review

Abstract: Water treatment is one of the most important issues for all walks of life around the world. Different from the conventional water treatment technology, the advanced power electronic pulse technology has unique features and advantages for the modern water treatment. Unfortunately, there is no literature reported to describe them in a comprehensive and systematic way. To fill this gap, an overview of modern power electronic pulse generators (PPGs) for water treatment is presented. This article, for the first time, classifies the different types of PPGs from the viewpoint of pulse formation. Each of them is discussed, and the advantages and disadvantages are compared and summarized. Aside from that, this article presents the development and trend of the pulse generators suitable for the specified water treatment processes such as electrolysis, sterilization, and discharge degradation. Finally, a list of more than 100 relevant technical papers is also appended for a quick reference.

Effects of Hafnium Oxide on Surface Potential and Drain Current Models for Subthreshold Short Channel Metal–Oxide–Semiconductor-Field-Effect-Transistor

Abstract: Surface potential and drain current models for a physically based double halo metal–oxide–semiconductor-field-effect-transistor (MOSFET) are reported. The proposed models have been established in sub-threshold mode of MOSFET operation. The depletion layer depth used in the pseudo two dimensional Poisson’s equation comprises the effect of two symmetrical pocket implantations at both the ends of the channel region. In this effort, improvement in the investigation is brought in by taking lateral asymmetric channel owing to non-uniform doping. The conventional silicon-dioxide (SiO2) material is replaced with a promising high-k dielectric material hafnium oxide (HfO2) to analyze the surface potential and drain current models. Analytical results have been compared using Synopsys technology computer aided design (TCAD). Excellent conformities between the analytical models and simulations are observed.

An insight to the performance of vertical super-thin body (VSTB) FET in presence of interface traps and corresponding noise and RF characteristics

Abstract: We investigated vertical super-thin body (VSTB) FET performance in presence of different interface (HfO2/Si) trap distributions (uniform and Gaussian) and concentrations using TCAD tools. For trap concentration (TC) of 1013 eV−1 cm−2, the percentage change in on-to-off current ratio (Ion/Ioff) is 93.91% for uniform trap (UT) and 49.8% for Gaussian trap (GT) distribution. For the same TC, subthreshold swing (SS) shows percentage change of 5.1% for UT and 11.41% for GT distribution. Thus, the device performance shows good immunity for TC up to 1013 eV−1 cm−2. However, for TC = 1014 eV−1 cm−2 SS degrades significantly. The influence of traps on the cumulative effect of three noise sources (diffusion + generation–recombination/G–R + flicker) and on individual noise sources (G–R and diffusion) is explained qualitatively at low and high frequencies (f = 1 MHz and 10 GHz). The study shows that the overall noise cannot disturb the device performance at very high frequency. Various radio-frequency (RF) parameters like transconductance (gm), total input capacitance (Cgg), gate-drain capacitance (Cgd), unit-gain cutoff frequency (fT), and gain–bandwidth-product (GBP) are also studied for variation of trap types. For TC = 1014 eV−1 cm−2, the percentage change in fTmax (GBPmax) is − 21.43% (− 8%) for UT and − 22.86% (− 9.6%) for GT distribution.

A methodology for designing LVDS interface system

Abstract: In this paper, a complete transmitter has been designed using low-voltage differential signaling (LVDS) technology. It is a new analog technology based on the serial I/O interface data communications. The complete transmitter circuit consists of driver, cascode current mirror circuit, pseudo random binary sequence (PRBS), and electrostatic discharge (ESD) pad. Here, transmitter is designed initially, and its biasing has been done using cascode current mirror. The layout parameter variation approach has been used to design ESD protection circuit for transmitter. An effort was made to reduce the parasitic capacitance and parasitic resistance. It helps to improve the performance of transmitter and reducing electrostatic discharge issues. The complete system has been designed using 0.18 μm CMOS technology at 1.8 V. The data rate of 2 Gbps and power consumption of 6.3 mW has been achieved using Cadence virtuoso PDK of Silatera Malaysia.