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Author

Dimitrios Schinianakis

Other affiliations: Bell Labs
Bio: Dimitrios Schinianakis is an academic researcher from University of Patras. The author has contributed to research in topics: Elliptic curve cryptography & Elliptic curve point multiplication. The author has an hindex of 9, co-authored 19 publications receiving 413 citations. Previous affiliations of Dimitrios Schinianakis include Bell Labs.

Papers
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Journal ArticleDOI
TL;DR: A hardware architecture of an elliptic Curve point multiplier is proposed that exploits the intrinsic parallelism of the residue number system (RNS), in order to speed up the elliptic curve point calculations and minimize the area complexity of the elliptIC curve point multiplier.
Abstract: Elliptic curve point multiplication is considered to be the most significant operation in all elliptic curve cryptography systems, as it forms the basis of the elliptic curve discrete logarithm problem. Designs for elliptic curve cryptography point multiplication are area demanding and time consuming. Thus, the efficient realization of point multiplication is of fundamental importance for the performance of an elliptic curve system. In this paper, a hardware architecture of an elliptic curve point multiplier is proposed that exploits the intrinsic parallelism of the residue number system (RNS), in order to speed up the elliptic curve point calculations and minimize the area complexity of the elliptic curve point multiplier. The architecture proves to be the fastest among all known design approaches, while complexity is less than half of that of previous efforts. This architecture also supports the required input (binary-to-RNS) and output (RNS-to-binary) conversions. Through a graph-oriented approach, the area of the elliptic curve point multiplier is minimized, by optimizing the point addition and doubling algorithms. Also, through this approach, the number of execution steps for point addition is matched to the number of execution steps for point doubling. Additionally, the impact of various RNS bases, in terms of number of moduli and their bit lengths, on the area and speed of the proposed implementation is analyzed, in an effort to define the potential for using RNS in elliptic curve cryptography.

106 citations

Journal ArticleDOI
TL;DR: A new hardware architecture for ECPM over GF(p) is presented, based on the residue number system (RNS), which encompasses RNS bases with various word-lengths in order to efficiently implement RNS Montgomery multiplication.
Abstract: Elliptic curve point multiplication (ECPM) is one of the most critical operations in elliptic curve cryptography. In this brief, a new hardware architecture for ECPM over GF(p) is presented, based on the residue number system (RNS). The proposed architecture encompasses RNS bases with various word-lengths in order to efficiently implement RNS Montgomery multiplication. Two architectures with four and six pipeline stages are presented, targeted on area-efficient and fast RNS Montgomery multiplication designs, respectively. The fast version of the proposed ECPM architecture achieves higher speeds and the area-efficient version achieves better area-delay tradeoffs compared to state-of-the-art implementations.

85 citations

Journal ArticleDOI
TL;DR: The proposed processor employs extensive pipelining techniques for Karatsuba-Ofman method to achieve high throughput multiplication and supports the recommended NIST curve P256 and is based on an extended NIST reduction scheme.
Abstract: In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba–Ofman method to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high-throughput modular divider, which results in a short datapath for maximized frequency, are implemented. The processor supports the recommended NIST curve P256 and is based on an extended NIST reduction scheme. The proposed processor performs single-point multiplication employing points in affine coordinates in 2.26 ms and runs at a maximum frequency of 160 MHz in Xilinx Virtex 5 (XC5VLX110T) field-programmable gate array.

58 citations

Proceedings ArticleDOI
16 May 2006
TL;DR: A VLSI residue number system (RNS) architecture of an ECPM is presented and it is shown that such an application is feasible and that it leads to a significant improvement in the execution time of a scalar point multiplication.
Abstract: An elliptic curve point multiplier (ECPM) is the main part of all elliptic curve cryptography (ECC) systems and its performance is decisive for the performance of the overall cryptosystem. A VLSI residue number system (RNS) architecture of an ECPM is presented in this paper. In the proposed approach, the necessary mathematical conditions that need to be satisfied, in order to replace typical finite field circuits with RNS ones, are investigated. It is shown that such an application is feasible and that it leads to a significant improvement in the execution time of a scalar point multiplication.

51 citations

Journal ArticleDOI
TL;DR: An analysis of input/output conversions to/from residue representation, along with the proposed residue Montgomery multiplication algorithm, reveals common multiply-accumulate data paths both between the converters and between the two residue representations.
Abstract: A design methodology for incorporating Residue Number System (RNS) and Polynomial Residue Number System (PRNS) in Montgomery modular multiplication in GF(p) or GF(2n) respectively, as well as a VLSI architecture of a dual-field residue arithmetic Montgomery multiplier are presented in this paper. An analysis of input/output conversions to/from residue representation, along with the proposed residue Montgomery multiplication algorithm, reveals common multiply-accumulate data paths both between the converters and between the two residue representations. A versatile architecture is derived that supports all operations of Montgomery multiplication in GF(p) and GF(2n), input/output conversions, Mixed Radix Conversion (MRC) for integers and polynomials, dual-field modular exponentiation and inversion in the same hardware. Detailed comparisons with state-of-the-art implementations prove the potential of residue arithmetic exploitation in dual-field modular multiplication.

48 citations


Cited by
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Journal Article
TL;DR: In this article, a processor architecture for elliptic curves cryptosystems over fields GF(2 m ) is proposed, which is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curve and finite fields.
Abstract: This work proposes a processor architecture for elliptic curves cryptosystems over fields GF(2 m ) This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields The main features of this architecture are the use of an optimized bit-parallel squarer, a digit-serial multiplier, and two programmable processors Through reconfiguration, the squarer and the multiplier architectures can be optimized for any field order or field polynomial The multiplier performance can also be scaled according to system's needs Our results show that implementations of this architecture executing the projective coordinates version of the Montgomery scalar multiplication algorithm can compute elliptic curve scalar multiplications with arbitrary points in 021 msec in the field GF(2 167 ) A result that is at least 19 times faster than documented hardware implementations and at least 37 times faster than documented software implementations

205 citations

Book ChapterDOI
10 Aug 2008
TL;DR: Improved and novel implementations employing GPUs as accelerator for RSA and DSA cryptosystems as well as for Elliptic Curve Cryptography (ECC) are presented.
Abstract: Modern Graphics Processing Units (GPU) have reached a dimension with respect to performance and gate count exceeding conventional Central Processing Units (CPU) by far. Many modern computer systems include --- beside a CPU --- such a powerful GPU which runs idle most of the time and might be used as cheap and instantly available co-processor for general purpose applications. In this contribution, we focus on the efficient realisation of the computationally expensive operations in asymmetric cryptosystems on such off-the-shelf GPUs. More precisely, we present improved and novel implementations employing GPUs as accelerator for RSA and DSA cryptosystems as well as for Elliptic Curve Cryptography (ECC). Using a recent Nvidia 8800GTS graphics card, we are able to compute 813 modular exponentiations per second for RSA or DSA-based systems with 1024 bit integers. Moreover, our design for ECC over the prime field P-224 even achieves the throughput of 1412 point multiplications per second.

199 citations

01 Jan 2014
TL;DR: In this article, the authors proposed a method to improve the quality of the information provided by the user by using the information from the user's profile and the user profile of the service provider.
Abstract: Натрийуретические пептиды (НУП) являются важными биомаркерами в диагностике и определении прогноза у пациентов с сердечной недостаточностью (СН). Оценка динамики концентрации НУП (BNP, Nt -proBNP) может быть использована в качестве критерия успешности проводимой терапии. так, при достижении целевых уровней НУП можно прогнозировать благоприятный исход заболевания. В настоящее время лечение СН с учетом уровней НУП является частью рекомендаций по лечению СН (класс IIа) и улучшению ее исхода (класс IIб) в США, однако такой подход не используется в российских клиниках. Цель. Представить современный взгляд на возможность использования НУП для оценки эффективности проводимой терапии пациентов с СН. Ключевые слова: натрийуретические пептиды, сердечная недостаточность, оценка эффективности терапии.

167 citations

Journal ArticleDOI
TL;DR: A thorough study on the lightweight cryptography as a solution to the security problem of resource-constrained devices in IoT has been presented and it can be observed that AES and ECC are the most suitable for used lightweight cryptographic primitives.
Abstract: In Internet of Things (IoT), the massive connectivity of devices and enormous data on the air have made information susceptible to different type of attacks. Cryptographic algorithms are used to provide confidentiality and maintain the integrity of the information. But small size, limited computational capability, limited memory, and power resources of the devices make it difficult to use the resource intensive traditional cryptographic algorithms for information security. In this scenario it becomes impertinent to develop lightweight security schemes for IoT. A thorough study on the lightweight cryptography as a solution to the security problem of resource-constrained devices in IoT has been presented in this work. This paper is a comprehensive attempt to provide an in-depth and state of the art survey of available lightweight cryptographic primitives till 2019. In this paper 21 lightweight block ciphers, 19 lightweight stream ciphers, 9 lightweight hash functions and 5 variants of elliptic curve cryptography (ECC) has been discussed i.e. in total 54 LWC primitives are compared in their respective classes. The comparison of the ciphers has been carried out in terms of chip area, energy and power, hardware and software efficiency, throughput, latency and figure of merit (FoM). Based on the findings it can be observed that AES and ECC are the most suitable for used lightweight cryptographic primitives. Several open research problems in the field of lightweight cryptography have also been identified.

137 citations