Due to the severe cost pressure of consumer electronics, a migration to an advanced nanoscale CMOS processes, which is primarily developed for fast and low-power digital circuits operating at low supply voltages, is necessary, but it forces wireless RF transceivers to exploit more and more digital circuitry These basic CMOS properties tend to coerce the design of wireless functions towards the digital domain where transistors are utilized as switches rather than current sources Within the past decade, there have been tremendous efforts towards implementing fully-digital or digitally-intensive RF transmitters in which they demonstrate transmitter designs that operate from baseband up to the pre-power amplifier (PA) stage entirely in the digital domain In view of this digitalization, the RF transmitter modulator, being the nearest to the antenna as it converts digital baseband modulation samples into an RF waveform, is considered the most critical building block of the transmitter, and it can be in the form of either a polar, Cartesian (I/Q), or an outphasing topology For wide modulation bandwidths, due to their direct linear summation of the in-phase (I) and quadrature-phase (Q) signals and thus the avoidance of the bandwidth expansion, Cartesian modulators are substantiated as the most appropriate choice over their polar or outphasing counterparts Since the effective modulating sample resolution is the utmost important parameter as it directly impacts the achievable dynamic range, linearity, error vector magnitude (EVM), noise floor, and out-of-band spectral emission, this thesis proposes a wideband, high-resolution, all-digital orthogonal I/Q radio-frequency digital-to-analog (RF-DAC) Chapter 1 briefly provides an overview of the conventional RF radio building blocks It is discussed that contemporary RF transceivers must support most of multi-mode/multiband communication standards such as Wi-Fi, Bluetooth, and Fourth Generation (4G) of 3GPP cellular In Chapter 2, four types of RF transmitter architectures have been briefly described The analog I/Q modulators are the most straightforward and widely employed RF transmitters They are later replaced by analog polar counterparts to address their poor power efficiency and noise performance On the other hand, in the analog polar RF transmitters, their related amplitude and phase signals must be aligned or spectral regrowth is inevitable Utilizing digitally intensive polar RF transmitters mitigates the latter alignment issue Nonetheless, polar transmitters suffer from an additional issue that is related to their nonlinear conversion of in-phase and quadrature-phase signals into the amplitude and phase representation Therefore, the polar RF transmitters are not able to manage very large baseband bandwidth of the most stringent communication standards, therefore, reusing I/Q modulators based on digitally intensive implementation appears to be a reasonable approach to resolve this issue The digital I/Q RF transmitters, however, suffer again from inadequate power efficiency Moreover, the combination of in-phase and quadrature phase paths must be orthogonal to produce an undistorted-upconverted-modulated RF signal In Chapter 3, a novel all-digital I/Q RF modulator is described Employing an upconverting RF clock with a 25% duty cycle ensures the orthogonal summation of Ipath and Qpath, which avoids nonlinear signal distortion It was clarified that electric summing of I and Q digital unit array switches is the most appropriate I/Q orthogonal summation approach Moreover, to address all four quadrants of the constellation diagram, the differential quadrature upconverting RF clocks must be utilized In addition, it was explained that employing switches instead of utilizing current sources leads to superior noise performance of the all-digital I/Q transmitter In Chapter 4, a novel 2×3-bit all-digital I/Q (Cartesian) RF transmit modulator is implemented which operates as an RF-DAC The modulator performs based on the concept of orthogonal summing, which is introduced and elaborated in Chapter 3 It is based on a time-division duplexing (TDD) manner of an orthogonal I/Q addition By employing this method, a very simple and compact design featuring high-output power, power-efficiency and low-EVM has been realized The resolution of the experimental RF-DAC presented in this work is only 3-bit (including one sign bit), but it will be demonstrated in the following chapters that the resolution can be increased to 8–12 bits in an unequivocal manner for utilization in multi-standard wireless applications In Chapter 5, the system design considerations of the proposed high-resolution, wideband all-digital I/Q RF-DAC are discussed It is demonstrated that the upsampling clock frequency (fCKR), DRAC resolution (Nb), and memory length (lmem) are three important parameters that affect the dynamic performance of the proposed RF-DAC Based on system level simulation results and the limitation in implementing the RF-DAC test-chip, they are designated as fCKR=300 MHz, Nb=12 bit, and lmem=8 k-word The effect of these parameters on the in-band as well as out-of-band performance of RF-DAC are investigated It is concluded that exploiting 13 bits of resolution for quadrature baseband signals is sufficient to meet the most stringent communication requirements In Chapter 6, the theory and the design procedure of an innovative, differential, orthogonal power combining network, which is employed in the proposed all-digital modulator, is thoroughly explained It is demonstrated that, in order to maintain an orthogonal operation between the in-phase and quadrature-phase paths, the effect of the power combiner on the in-phase and quadrature-phase paths must be considered, otherwise, the linear summation will not occur As a result, the EVM and linearity performance will diminish The power combiner consists of a transformer balun as well as its related programmable primary and secondary shunt capacitors In order to achieve high efficiency at full power of operation, a class-E type matching network is adopted and subsequently modified in order to obtain a minimum modulation error A switchable cascode structure is exploited to mitigate a reliability issue as well as to perform a mixer operation Moreover, utilizing a switchable cascode structure also improves the isolation between quadrature paths Furthermore, it is explained that the power combiner efficiency is primarily related to the transformer balun efficiency A procedure is introduced in order to design an efficient, compact balun transformer Also, it is explained that the RF-DAC operates as a class-B power amplifier at the power back-off levels As a result, its performance in the power back-off region is lowered In Chapter 7, the implemented wideband, 2×13-bit I/Q RF-DAC-based all-digital modulator realized in 65-nm CMOS is presented Employing the orthogonal I/Q combining approach which is proposed in Chapter 3 guarantees the isolation between in-phase and quadrature-phase paths The 4×f0 off-chip single-ended clock is converted to a differential version employing an on-chip transformer The wide swing, low phase noise, high-speed dividers are incorporated to translate the 4×f0 differential clock to the fundamental frequency of f0 In the meantime, the complementary quadrature sign bit is used to address four quadrants of the related constellation diagram The 25% differential quadrature clocks are generated using logic-AND operation between 2×f0 differential clock and f0 differential quadrature clocks The 12-bit DRAC is implemented employing a segmentation approach, which consists of 256 MSB and 16 LSB thermometer unit cells The layout arrangement of the DRAC unit cell proves to be very crucial It was concluded that the vertical layout would be the most appropriate selection The LO leakage and I/Q image rejection technique as well as two DPD memoryless techniques of AM-AM/AM-PM and constellation mapping are introduced, which will be extensively utilized in the measurement segment In Chapter 8, the high-resolution wideband 2×13-bit all-digital I/Q transmitter, which was introduced in Chapter 7, is thoroughly measured First, the chip is tested in continuouswave mode operation It is demonstrated that, with a 13V supply and, of course, an on-chip power combiner, the RF-DAC chip generates more than 21dBm RF output power within a frequency range of 136–251 GHz The peak RF output power, overall system, and drain energy efficiencies of the modulator are 228 dBm, 34%, and 42%, respectively The measured static noise floor is below -160 dBc/Hz The digital I/Q RF modulator demonstrates an IQ image rejection and LO leakage of -65 dBc and -68 dBc, respectively The RF-DAC could be linearized employing either of the two digital predistortion (DPD) approaches: memoryless polynomial or a lookup table Its linearity is examined utilizing 4/16/64/256/1024-QAM baseband signals while their related modulation bandwidth can be as high as 154 MHz Using AM-AM/AM-PM DPD improves the linearity by more than 25 dB while the measured EVM is better than -28 dB Moreover, the constellation-mapping DPD is applied to the RF-DAC which improves linearity by more than 19 dB These numbers indicate that this innovative concept is a viable option for the next generations of multi band/multi-standard transmitters The realized demonstrator can perform as an energy-efficient RF-DAC in a stand-alone digital transmitter directly (eg, for WLAN) or as a pre-driver for high-power basestation PAs Chapter 9 draws the conclusions of the this thesis work and provides recommendations for future research and directions in the field of all-digital RF transmitters for wireless communication applications

All-Digital I/Q RF-DAC

Thank you for reading lte and the evolution to 4g wireless design and measurement challenges. Maybe you have knowledge that, people have search hundreds times for their favorite books like this lte and the evolution to 4g wireless design and measurement challenges, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they cope with some malicious bugs inside their desktop computer.

Lte And The Evolution To 4g Wireless Design And Measurement Challenges

Medical imaging plays a significant role in different clinical applications such as medical procedures used for early detection, monitoring, diagnosis, and treatment evaluation of various medical conditions. Basicsof the principles and implementations of artificial neural networks and deep learning are essential for understanding medical image analysis in computer vision. Deep Learning Approach (DLA) in medical image analysis emerges as a fast-growing research field. DLA has been widely used in medical imaging to detect the presence or absence of the disease. This paper presents the development of artificial neural networks, comprehensive analysis of DLA, which delivers promising medical imaging applications. Most of the DLA implementations concentrate on the X-ray images, computerized tomography, mammography images, and digital histopathology images. It provides a systematic review of the articles for classification, detection, and segmentation of medical images based on DLA. This review guides the researchers to think of appropriate changes in medical image analysis based on DLA.

/pdf/medical-image-analysis-based-on-deep-learning-approach-gegeq5b2wv.pdf

Medical image analysis based on deep learning approach.

In terms of growth, effect, and capability, the 5G-enabled Internet of Things (IoT) is incredible. The volume of data distributed and processed by IoT (Internet of Things) systems that trust connectivity and coverage raises some security problems. As IoT technology is directly used in our daily lives, the threats of present cyberspace may grow more prominent globally. Extended network life, coverage, and connectivity are all required for securing IoT-based 5G network devices. As a result of these failures, there are flaws that lead to security breaches. Because purposeful faults can quickly render the entire network dysfunctional, they are more difficult to identify than unexpected failures. Securing IoT-based 5G Network Device Connectivity and Coverage for expending Encryption and Authentication Scheme (EAS) framework is proposed in this study, which uses novel security flaws. In this research, we proposed a Boltzmann machine (BMKG)-based encryption algorithm for securing 5G-enabled IoT device network environment and compared various asymmetric algorithms for key exchange.

/pdf/securing-5g-iot-device-connectivity-and-coverage-using-49ankdemkj.pdf

Securing 5G-IoT Device Connectivity and Coverage Using Boltzmann Machine Keys Generation

This paper presents a statistical feature approach in fully convolutional time series classification (TSC), which is aimed at improving the accuracy and efficiency of TSC. This method is based on fully convolutional neural networks (FCN), and there are the following two properties: statistical features in data preprocessing and fine-tuning strategies in network training. The key steps are described as follows: firstly, by the window slicing principle, dividing the original time series into multiple equal-length subsequences; secondly, by extracting statistical features on each subsequence, in order to form a new sequence as the input of the neural network, and training neural network by the fine-tuning idea; thirdly, by evaluating the classification performance about test sets; and finally, by comparing the sample sequence complexity and network classification loss accuracy with the FCN using the original sequence. Our experimental results show that the proposed method improved the classification effects of FCN and the residual network (ResNet), which means that it has a generalization ability to the network structures.

/pdf/time-series-classification-based-on-statistical-features-4bl7al4huz.pdf

Time series classification based on statistical features

/pdf/rf-front-end-circuits-and-architectures-for-iot-lte-a-5g-4nu1mspwe9.pdf

RF Front-End Circuits and Architectures for IoT/LTE-A/5G Connectivity

This paper describes a high-speed CORDIC-based digital outphasing modulator. Fixed-point Matlab model of the outphasing modulator is developed to evaluate the system performance and define the circuit design parameters. Design issues such as signal quantization error, delay mismatch, and phase overflowing are addressed to enable hardware implementation. The complete outphasing modulator is fully custom designed in 40 nm CMOS, which can be integrated in a millimeter-wave outphasing transmitter to enhance the system average efficiency. Tested with 10.56 Gb/s 64-QAM, this work achieves an EVM of 3.2% and fulfils the IEEE 802.11ad spectral mask requirements.

/pdf/cordic-based-multi-gb-s-digital-outphasing-modulator-for-ivqvn2lz58.pdf

CORDIC-Based Multi-Gb/s Digital Outphasing Modulator for Highly Efficient Millimeter-Wave Transmitters

This paper describes a fully integrated power amplifier (PA) in 100 nm InGaAs pHEMT process for E-band point-to-point communications. The device size and biasing conditions are optimized to enhance the overall performance at millimeter-wave frequencies. The complete PA consists of two unit PAs and each unit PA has four stages to improve the gain while ensuring stability from dc to the operating frequencies. A 4-way zero-degree combiner (in the unit PA) and a 2-way λ/2 combiner are used to boost the output power. Occupying 5 mm2, the proposed PA achieves an output power of 0.45 W with 17.9% PAE at 74 GHz.

/pdf/a-0-45-w-18-pae-e-band-power-amplifier-in-100-nm-ingaas-4xpa2cpbts.pdf

Dixian Zhao

Papers

RF Front-End Circuits and Architectures for IoT/LTE-A/5G Connectivity

CORDIC-Based Multi-Gb/s Digital Outphasing Modulator for Highly Efficient Millimeter-Wave Transmitters

A 0.45 W 18% PAE E-Band Power Amplifier in 100 nm InGaAs pHEMT Technology