Dominique Carisetti

Bio: Dominique Carisetti is an academic researcher from Philips. The author has contributed to research in topics: Transistor & High-electron-mobility transistor. The author has an hindex of 7, co-authored 17 publications receiving 183 citations.

Thermal Characterization Using Optical Methods of AlGaN/GaN HEMTs on SiC Substrate in RF Operating Conditions

Abstract: Performance and reliability of wide bandgap high-power amplifiers are correlated with their thermal behavior. Thermal model development and suitable temperature measurement systems are necessary to quantify the channel temperature of devices in real operating conditions. As a direct temperature measurement within a channel is most of the time not achievable, the common approach is to measure the device temperature at different locations close to the hotspot and then to use simulations to estimate the channel temperature. This paper describes a complete thermal characterization of AlGaN/gallium nitride (GaN) on silicon carbide high electron-mobility transistors (HEMTs) when devices are operating in dc bias, pulsed, and continuous wave. Infrared thermography, charge-coupled device-based thermoreflectance microscopy, and micro-Raman spectroscopy have been performed to extract the thermal resistance of the components. Results have been compared with simulations using a 3-D finite-element model to estimate the operating channel temperature. Measurements have shown that the RF-biased thermal resistance and the dc-biased thermal resistance of GaN HEMTs are similar.

Method of manufacturing by autoalignment an integrated semiconductor device comprising at least the formation of an encapsulated first electrode contact provided with spacers and of a second autoaligned electrode contact on the former

Abstract: A method of manufacturing by autoalignment an integrated semiconductor device is set forth comprising the realization on respective semiconductor layers of a first encapsulated electrode contact E provided with spacers and of a second autoaligned electrode contact B on the first contact thus equipped, which process comprises at least: a 0 ) the formation of a first and a second semiconductor layer for receiving the first and the second electrode contact, respectively; b 0 ) the formation by a so-called image reversal method of an opening B o with overhanging sides in a photoresist layer deposited on the first semiconductor layer; c 0 ) the deposition of a first metal layer forming the first electrode contact E in this opening, which contact has sides F 2 of a lower height than those F 1 of the photoresist layer, these sides F 2 having upper edges which are situated laterally at a small distance from the overhanging sides F 1 of the opening, thus leaving an aperture around the base of the first contact; d 0 ) the deposition of a first dielectric layer of a thickness greater than the value of the said small distance, which dielectric layer encapsulates the first contact without filling up the aperture; e 0 ) the lift-off of the dielectric and metallic layers around the first contact E, which remains encapsulated; f 0 ) the realization of spacers around the first encapsulated contact E.

1/f Noise Sources

Abstract: This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

Electronic surface and dielectric interface states on GaN and AlGaN

Abstract: GaN and AlGaN have shown great potential in next-generation high-power electronic devices; however, they are plagued by a high density of interface states that affect device reliability and performance, resulting in large leakage current and current collapse. In this review, the authors summarize the current understanding of the gate leakage current and current collapse mechanisms, where awareness of the surface defects is the key to controlling and improving device performance. With this in mind, they present the current research on surface states on GaN and AlGaN and interface states on GaN and AlGaN-based heterostructures. Since GaN and AlGaN are polar materials, both are characterized by a large bound polarization charge on the order of 1013 charges/cm2 that requires compensation. The key is therefore to control the compensation charge such that the electronic states do not serve as electron traps or affect device performance and reliability. Band alignment modeling and measurement can help to determi...

AlGaN/GaN High-Electron-Mobility Transistors Fabricated Through a Au-Free Technology

Abstract: This letter reports undoped AlGaN/GaN high-electron-mobility transistors (HEMTs) fabricated with a Si-CMOS-compatible technology based on Ti/Al/W ohmic and Schottky contacts. The use of ohmic recess is key to reduce the contact resistance of this Au-free metallization below 0.5 Ω·mm. Comparison of HEMTs fabricated on the same wafer with and without ohmic recess shows that the recess provides a tenfold reduction in contact resistance, resulting in a fivefold lower forward voltage drop at IDS = 100 mA/mm. The reported Au-free AlGaN/GaN HEMT fabrication technology provides similar performance (i.e., contact resistance, leakage current, and breakdown voltage) than state-of-the-art Au-based AlGaN/GaN HEMTs and can be used in standard Si fabs without the risk of contamination.

Breakdown mechanisms in AlGaN/GaN HEMTs: An overview

Abstract: This paper reviews the physical mechanisms responsible for breakdown current in AlGaN/GaN high electron mobility transistors (HEMTs). Through a critical comparison between experimental data and previously published results we describe the following mechanisms, which can be responsible for the increase in drain current at high drain voltage levels, in the off-state: (i) source–drain breakdown, due to punch-through effects and/or to a poor depletion of the buffer; (ii) vertical (drain-bulk) breakdown, which can be particularly prominent when the devices are grown on a silicon substrate; (iii) breakdown of the gate–drain junction, due either to surface conduction mechanisms or to conduction through the (reverse-biased) Schottky junction at the gate; (iv) impact ionization triggered by hot electrons, that may induce an increase in drain current due to the lowering of the barrier for the injection of electrons from the source.