Author
Dustin Z. Austin
Other affiliations: Lam Research
Bio: Dustin Z. Austin is an academic researcher from Oregon State University. The author has contributed to research in topics: Atomic layer deposition & Insulator (electricity). The author has an hindex of 6, co-authored 11 publications receiving 91 citations. Previous affiliations of Dustin Z. Austin include Lam Research.
Papers
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TL;DR: In this paper, the atomic layer deposition (ALD) processes for ruthenium (Ru) and Ru oxide (RuO2) using a zero-oxidation state liquid precursor, η4-2,3-dimethylbutadiene (Ru(DMBD)(CO)3), were reported.
Abstract: Atomic layer deposition (ALD) processes are reported for ruthenium (Ru) and ruthenium oxide (RuO2) using a zero-oxidation state liquid precursor, η4-2,3-dimethylbutadiene ruthenium tricarbonyl [Ru(DMBD)(CO)3]. Both ALD Ru and RuO2 films were deposited using alternating N2 -purge-separated pulses of Ru(DMBD)(CO)3 and O2. ALD Ru metal films were deposited via short (2 s) pulses of O2. Ru films have an ALD temperature window from 290 to 320 °C with a GPC of 0.067 nm/cycle and a negligible nucleation delay on SiO2. Ru films show a strong hexagonal crystal structure with low resistivity of approximately 14 μΩ cm at 320 °C. RuO2 films were deposited using longer (20 s) pulses of either molecular O2 or O2 plasma. RuO2 films deposited via thermal ALD using molecular O2 have a temperature window from 220 to 240 °C with a GPC and nucleation delay on SiO2 of 0.065 nm/cycle and 35 cycles, respectively. Thermal ALD RuO2 films show a distinct rutile phase microstructure with a resistivity of approximately 62 μΩ cm. In ...
46 citations
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TL;DR: In this article, the authors present a review of high-k and low-k dielectric materials and their application in various metal-insulator-metal (MIM) structures such as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements.
Abstract: High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges.We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling.We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful”requirements for the various enabling dielectric hard mask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements.We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.© 2019 The Electrochemical Society.
24 citations
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TL;DR: In this article, the cancelling effect between the positive quadratic voltage coefficient of capacitance (VCC) of Al2O3 and the negative VCC of SiO2 was employed to achieve the International Technology Roadmap for Semiconductors 2020 projections for capacitance, leakage current density, and voltage nonlinearity.
Abstract: Metal–insulator–insulator–metal (MIIM) capacitors with bilayers of Al2O3 and SiO2 are deposited at 200 °C via plasma enhanced atomic layer deposition. Employing the cancelling effect between the positive quadratic voltage coefficient of capacitance ( $\alpha $ VCC) of Al2O3 and the negative $\alpha $ VCC of SiO2, devices are made that simultaneously meet the International Technology Roadmap for Semiconductors 2020 projections for capacitance density, leakage current density, and voltage nonlinearity. Optimized bilayer Al2O3/SiO2 MIIM capacitors exhibit a capacitance density of 10.1 fF/ $\mu \text{m}^{2}$ , a leakage current density of 6.8 nA/cm $^{2}$ at 1 V, and a minimized $\alpha $ VCC of −20 ppm/ $\text{V}^{2}$ .
14 citations
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TL;DR: In this paper, the influence of the metal/dielectric interface, in the absence of a significant interfacial layer oxide (ILO), on the voltage nonlinearity of capacitance for metal-insulator-metal capacitors was examined.
Abstract: Metals with low enthalpy of oxide formation (ΔHox) are used to examine the influence of the metal/dielectric interface, in the absence of a significant interfacial layer oxide (ILO), on the voltage nonlinearity of capacitance for metal-insulator-metal capacitors. For both atomic layer deposited Al2O3 and HfO2 dielectrics, Ag electrode devices show the lowest quadratic electric field coefficient of capacitance (αECC), followed in increasing order by Au, Pd, and Ni. The difference between the metals is greater for thinner dielectrics, which is consistent with increased influence of the interface. In addition, with decreasing dielectric thickness the quadratic voltage field coefficient of capacitance increases, whereas αECC decreases. It is proposed that the thickness dependencies are due to an interaction between vertical compression of the dielectric under an applied bias and the concomitant lateral expansion induced stress that is concentrated near the interface. Through this interaction, the metal interf...
10 citations
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TL;DR: In this article, Bismuth oxide thin films were deposited by atomic layer deposition using Bi(OCMe2iPr)3 and H2O at deposition temperatures between 90 and 270°C on Si3N4, TaN, and TiN substrates.
Abstract: Bismuth oxide thin films were deposited by atomic layer deposition using Bi(OCMe2iPr)3 and H2O at deposition temperatures between 90 and 270 °C on Si3N4, TaN, and TiN substrates. Films were analyzed using spectroscopic ellipsometry, x-ray diffraction, x-ray reflectivity, high-resolution transmission electron microscopy, and Rutherford backscattering spectrometry. Bi2O3 films deposited at 150 °C have a linear growth per cycle of 0.039 nm/cycle, density of 8.3 g/cm3, band gap of approximately 2.9 eV, low carbon content, and show the β phase structure with a (201) preferred crystal orientation. Deposition temperatures above 210 °C and postdeposition anneals caused uneven volumetric expansion, resulting in a decrease in film density, increased interfacial roughness, and degraded optical properties.
9 citations
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TL;DR: Damascene copper electroplating for on-chip interconnections, a process that was conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition as discussed by the authors.
Abstract: Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.
1,006 citations
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TL;DR: This review introduces the progress made in ALD, both for computational and experimental methodologies, and provides an outlook of this emerging technology in comparison with other film deposition methods.
245 citations
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01 Jan 2019
TL;DR: This tutorial clarifies the axiomatic definition of (v(α); i(β)) circuit elements via a lookup table dubbed an A-pad, of admissible (v; i) signals measured via Gedanken probing circuits.
Abstract: This tutorial clarifies the axiomatic definition of (v(α); i(β)) circuit elements via a lookup table dubbed an A-pad, of admissible (v; i) signals measured via Gedanken probing circuits. The (v(α); i(β)) elements are ordered via a complexity metric. Under this metric, the memristor emerges naturally as the fourth element, characterized by a state-dependent Ohm's law. A logical generalization to memristive devices reveals a common fingerprint consisting of a dense continuum of pinched hysteresis loops whose area decreases with the frequency ω and tends to a straight line as ω ~ ∞, for all bipolar periodic signals and for all initial conditions. This common fingerprint suggests that the term memristor be used hence-forth as a moniker for memristive devices.
242 citations
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TL;DR: The critical process parameters and the designing methodology of the specialized equipment required in food processing are described as a guide for the designers and the researchers of this technology.
Abstract: Background Pulsed electric field (PEF) is an attractive and efficient non-thermal technology that can advance functionality, extractability, and retrieval of nutritionally beneficial compounds. For industrial PEF food processing, high electric field consistency is of importance for continuous operation and an economical return-of-investment within a short period. Scope and approach The technology uptake at an industrial scale is still low due to the shortage of reliable and more practical electrical systems. Therefore, designing an application-specific and cost-effective electrical system is essential for commercial use of this novel technology. This review describes the requirements and developments of the electrical systems employed in PEF food processing. Key findings and conclusion The process parameters and control variables of the PEF system are not only critical for the designing of the electrical systems but also for the experts of the food sciences. Inadequate or insufficient description of different engineering aspects of experimental procedures is a hindrance in allowing the work to be reproduced in other laboratories. This review describes the critical process parameters and the designing methodology of the specialized equipment required in food processing as a guide for the designers and the researchers of this technology.
83 citations