E.A. Hijzen

Bio: E.A. Hijzen is an academic researcher. The author has contributed to research in topics: Noise figure & RFIC. The author has an hindex of 1, co-authored 1 publications receiving 5 citations.

Impact of downscaling and poly-gate depletion on the RF noise parameters of advanced nMOS transistors

Abstract: For the first time, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed. Based on measurements and physical device simulations we quantify the increasing danger of poly gate depletion with downscaling on the RF noise parameters of CMOS devices. While poly depletion does not affect the minimum noise figure, it results in a degradation of the noise matching freedom for RFIC designers. This trend worsens with technology downscaling.

Microwave Noise and FET Devices

Abstract: In this article, a short presentation of available FET technologies (GaAs MESFET, ΠI-V HEMT, and silicon CMOS) has been presented. Why minimum NF is suitable to benchmark different low-noise technologies has been discussed. Following this, basic concepts related to thermal noise in FETs and the reason why such technologies feature outstanding low-noise performance was illustrated/ and a short survey of minimum NF evolution has been presented. InP HEMT technology undoubtedly constitutes the best low-noise technology (especially to address applications in W or G Band). The noise performance of silicon MOSFET technology/ which is widely used in many applications because of its low cost, does not outperform that of GaAs pHEMT technology/ unless channel engineering is performed.

RF Noise of 65-nm MOSFETs in the Weak-to-Moderate-Inversion Region

Abstract: In this letter, the RF noise performance of 65-nm MOSFETs with 60-, 90-, 130-, and 240-nm drawn gate lengths has been extensively investigated in the weak-to-moderate-inversion region for low-power and low-voltage (LPLV) applications. Noise measurements show that although the noise performance is directly related to gate length (Lg), it does not monotonically scale with the inverse of gate length. When biased in the weak-inversion region, a transistor with slightly relaxed gate length, instead of minimum gate length, will benefit from a smaller gate resistance and a smaller equivalent noise resistance Rn. The transistor transconductance (gm), output conductance (gd), unity current gain frequency (fT) , maximum frequency of oscillation (f max), and noise parameters are extracted as a function of the drain current density and compared among devices with different gate lengths.

On the Number of Noise Parameters for Analyses of Circuits With MOSFETs

Abstract: The inequality relating Fmin and Lange invariant N for any noisy linear two-port network has been known since the 1980s. However, the applicability of this inequality to MOSFETs is not discussed in the literature, and thus, this inequality is not normally treated in analyses and designs of circuits based on MOSFETs. This work shows that by using N, the number of noise parameters required to model high-frequency noise of intrinsic MOSFETs can be reduced by one. This reduction in the noise parameters simplifies the noise correlation matrices, which leads to simpler noise factor expressions. A new set of noise correlation matrices and noise factor expressions is presented. These are expected to ease circuit optimizations of low-noise amplifiers and other circuits based on intrinsic MOSFET models.

Gate-stack analysis for 45-nm CMOS devices from an RF perspective

Abstract: Three gate stacks for the 45-nm node are analyzed from an RF perspective. The authors present an expression of the gate resistance valid for all three stacks, quantify the differences each stack has on several small-signal RF figures-of-merit and on the RF noise parameters, and demonstrate that devices with fully silicided gates will enable ultralow-power/low-noise RF applications, while the performance of transistors using multilayer gate stacks are limited by large contact resistance. Although offering better bandwidth and noise characteristics than the poly/silicide stack, the deposited metal stack will lose its advantage in devices requiring higher gate work functions than in planar bulk CMOS transistors.