E. Felt

Abstract: A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach.

Abstract: This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

Abstract: As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper defines noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with on-chip interconnect are also considered. This paper concludes with a discussion of the device, circuit, layout, and logic design issues associated with noise.

Abstract: The electronics industry is increasingly focused on the consumer marketplace, which requires low-cost high-volume products to be developed very rapidly. This, combined with advances in deep submicrometer technology have resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is increasingly likely that the chip will contain both analog and digital sections. Developing these mixed-signal (MS) systems-on-chip presents enormous challenges both to the designers of the chips and to the developers of the computer-aided design (CAD) systems that are used during the design process. This paper presents many of the issues that act to complicate the development of large single-chip MS systems and how CAD systems are expected to develop to overcome these issues.

Abstract: A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

Abstract: This paper presents a computer-aided design tool, IPRAIL, which automatically retargets existing analog layouts for technology migration and new design specifications. The reuse-based methodology adopted in IPRAIL utilizes expert designer knowledge embedded in analog layouts. IPRAIL automatically extracts analog layout intellectual properties as templates, incorporates new technology design rules and device sizes, and generates fully functional layouts. This is illustrated by retargeting two practical operational amplifier layouts from the TSMC 0.25 µm CMOS process to the TSMC 0.18 µm CMOS process. While manual re-design is known to take days to weeks, IPRAIL only takes minutes and achieves comparable circuit performances.